25 	void (*submit_command)(ctlr_info_t *h, CommandList_struct *c);
26 	void (*set_intr_mask)(ctlr_info_t *h, unsigned long val);
27 	unsigned long (*fifo_full)(ctlr_info_t *h);
28 	bool (*intr_pending)(ctlr_info_t *h);
29 	unsigned long (*command_completed)(ctlr_info_t *h);
220 static void SA5_submit_command( ctlr_info_t *h, CommandList_struct *c)   in SA5_submit_command()  argument
224 			h->ctlr, c->busaddr);  in SA5_submit_command()
226          writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);  in SA5_submit_command()
227 	readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);  in SA5_submit_command()
228 	 h->commands_outstanding++;  in SA5_submit_command()
229 	 if ( h->commands_outstanding > h->max_outstanding)  in SA5_submit_command()
230 		h->max_outstanding = h->commands_outstanding;  in SA5_submit_command()
238 static void SA5_intr_mask(ctlr_info_t *h, unsigned long val)  in SA5_intr_mask()  argument
242 		h->interrupts_enabled = 1;  in SA5_intr_mask()
243 		writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_intr_mask()
244 		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_intr_mask()
247 		h->interrupts_enabled = 0;  in SA5_intr_mask()
249 			h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_intr_mask()
250 		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_intr_mask()
258 static void SA5B_intr_mask(ctlr_info_t *h, unsigned long val)  in SA5B_intr_mask()  argument
262 		h->interrupts_enabled = 1;  in SA5B_intr_mask()
263                 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5B_intr_mask()
264 		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5B_intr_mask()
267 		h->interrupts_enabled = 0;  in SA5B_intr_mask()
269                         h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5B_intr_mask()
270 		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5B_intr_mask()
275 static void SA5_performant_intr_mask(ctlr_info_t *h, unsigned long val)  in SA5_performant_intr_mask()  argument
278 		h->interrupts_enabled = 1;  in SA5_performant_intr_mask()
279 		writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_performant_intr_mask()
280 		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_performant_intr_mask()
282 		h->interrupts_enabled = 0;  in SA5_performant_intr_mask()
284 				h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_performant_intr_mask()
285 		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_performant_intr_mask()
293 static unsigned long SA5_fifo_full(ctlr_info_t *h)  in SA5_fifo_full()  argument
295 	if( h->commands_outstanding >= h->max_commands)  in SA5_fifo_full()
305 static unsigned long SA5_completed(ctlr_info_t *h)  in SA5_completed()  argument
308 		= readl(h->vaddr + SA5_REPLY_PORT_OFFSET);  in SA5_completed()
311 		h->commands_outstanding--;  in SA5_completed()
327 static unsigned long SA5_performant_completed(ctlr_info_t *h)  in SA5_performant_completed()  argument
334 	register_value = readl(h->vaddr + SA5_OUTDB_STATUS);  in SA5_performant_completed()
336 	if (!(h->msi_vector || h->msix_vector)) {  in SA5_performant_completed()
337 		writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);  in SA5_performant_completed()
341 		register_value = readl(h->vaddr + SA5_OUTDB_STATUS);  in SA5_performant_completed()
344 	if ((*(h->reply_pool_head) & 1) == (h->reply_pool_wraparound)) {  in SA5_performant_completed()
345 		register_value = *(h->reply_pool_head);  in SA5_performant_completed()
346 		(h->reply_pool_head)++;  in SA5_performant_completed()
347 		h->commands_outstanding--;  in SA5_performant_completed()
352 	if (h->reply_pool_head == (h->reply_pool + h->max_commands)) {  in SA5_performant_completed()
353 		h->reply_pool_head = h->reply_pool;  in SA5_performant_completed()
354 		h->reply_pool_wraparound ^= 1;  in SA5_performant_completed()
362 static bool SA5_intr_pending(ctlr_info_t *h)  in SA5_intr_pending()  argument
365 		readl(h->vaddr + SA5_INTR_STATUS);  in SA5_intr_pending()
377 static bool SA5B_intr_pending(ctlr_info_t *h)  in SA5B_intr_pending()  argument
380                 readl(h->vaddr + SA5_INTR_STATUS);  in SA5B_intr_pending()
389 static bool SA5_performant_intr_pending(ctlr_info_t *h)  in SA5_performant_intr_pending()  argument
391 	unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);  in SA5_performant_intr_pending()
396 	if (h->msi_vector || h->msix_vector)  in SA5_performant_intr_pending()
400 	register_value = readl(h->vaddr + SA5_OUTDB_STATUS);  in SA5_performant_intr_pending()