Lines Matching refs:reg_write
488 static inline void reg_write(const struct lanai_dev *lanai, u32 val, in reg_write() function
498 reg_write(lanai, lanai->conf1, Config1_Reg); in conf1_write()
503 reg_write(lanai, lanai->conf2, Config2_Reg); in conf2_write()
519 reg_write(lanai, 0, Reset_Reg); in reset_board()
1063 reg_write(lanai, i, IntControlEna_Reg); in intr_enable()
1068 reg_write(lanai, i, IntControlDis_Reg); in intr_disable()
1274 reg_write(lanai, (ptr << 12) | lvcc->vci, Butt_Reg); in lanai_endtx()
1574 reg_write(lanai, INT_ALL, IntAck_Reg); in lanai_reset()
1594 reg_write(lanai, 0, ServWrite_Reg); in service_buffer_allocate()
1596 reg_write(lanai, in service_buffer_allocate()
1725 reg_write(lanai, wreg, ServRead_Reg); in run_service()
1877 reg_write(lanai, ack, IntAck_Reg); in lanai_int_1()
2098 reg_write(lanai, pcr_to_cbricg(&lanai->cbrvcc->qos), CBR_ICG_Reg); in lanai_cbr_setup()
2099 reg_write(lanai, lanai->cbrvcc->vci, CBR_PTR_Reg); in lanai_cbr_setup()
2154 reg_write(lanai, lanai->conf1 | CONFIG1_GPOUT1, Config1_Reg); in lanai_dev_open()
2179 reg_write(lanai, lanai->conf1 | CONFIG1_GPOUT1, Config1_Reg); in lanai_dev_open()
2200 reg_write(lanai, TX_FIFO_DEPTH, TxDepth_Reg); in lanai_dev_open()
2201 reg_write(lanai, 0, CBR_ICG_Reg); /* CBR defaults to no limit */ in lanai_dev_open()