Lines Matching refs:iadev
73 static void desc_dbg(IADEV *iadev);
575 IADEV *iadev; in ia_cbrVc_close() local
579 iadev = INPH_IA_DEV(vcc->dev); in ia_cbrVc_close()
580 iadev->NumEnabledCBR--; in ia_cbrVc_close()
581 SchedTbl = (u16*)(iadev->seg_ram+CBR_SCHED_TABLE*iadev->memSize); in ia_cbrVc_close()
582 if (iadev->NumEnabledCBR == 0) { in ia_cbrVc_close()
583 writew((UBR_EN | ABR_EN | (0x23 << 2)), iadev->seg_reg+STPARMS); in ia_cbrVc_close()
587 for (i=0; i < iadev->CbrTotEntries; i++) in ia_cbrVc_close()
590 iadev->CbrRemEntries++; in ia_cbrVc_close()
599 static int ia_avail_descs(IADEV *iadev) { in ia_avail_descs() argument
601 ia_hack_tcq(iadev); in ia_avail_descs()
602 if (iadev->host_tcq_wr >= iadev->ffL.tcq_rd) in ia_avail_descs()
603 tmp = (iadev->host_tcq_wr - iadev->ffL.tcq_rd) / 2; in ia_avail_descs()
605 tmp = (iadev->ffL.tcq_ed - iadev->ffL.tcq_rd + 2 + iadev->host_tcq_wr - in ia_avail_descs()
606 iadev->ffL.tcq_st) / 2; in ia_avail_descs()
612 static int ia_que_tx (IADEV *iadev) { in ia_que_tx() argument
616 num_desc = ia_avail_descs(iadev); in ia_que_tx()
618 while (num_desc && (skb = skb_dequeue(&iadev->tx_backlog))) { in ia_que_tx()
630 skb_queue_head(&iadev->tx_backlog, skb); in ia_que_tx()
637 static void ia_tx_poll (IADEV *iadev) { in ia_tx_poll() argument
643 ia_hack_tcq(iadev); in ia_tx_poll()
644 while ( (rtne = ia_deque_rtn_q(&iadev->tx_return_q))) { in ia_tx_poll()
682 ia_enque_head_rtn_q (&iadev->tx_return_q, rtne); in ia_tx_poll()
694 ia_que_tx(iadev); in ia_tx_poll()
699 static void ia_eeprom_put (IADEV *iadev, u32 addr, u_short val)
721 t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS);
723 t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS);
735 static u16 ia_eeprom_get (IADEV *iadev, u32 addr) in ia_eeprom_get() argument
759 static void ia_hw_type(IADEV *iadev) { argument
760 u_short memType = ia_eeprom_get(iadev, 25);
761 iadev->memType = memType;
763 iadev->num_tx_desc = IA_TX_BUF;
764 iadev->tx_buf_sz = IA_TX_BUF_SZ;
765 iadev->num_rx_desc = IA_RX_BUF;
766 iadev->rx_buf_sz = IA_RX_BUF_SZ;
769 iadev->num_tx_desc = IA_TX_BUF / 2;
771 iadev->num_tx_desc = IA_TX_BUF;
772 iadev->tx_buf_sz = IA_TX_BUF_SZ;
774 iadev->num_rx_desc = IA_RX_BUF / 2;
776 iadev->num_rx_desc = IA_RX_BUF;
777 iadev->rx_buf_sz = IA_RX_BUF_SZ;
781 iadev->num_tx_desc = IA_TX_BUF / 8;
783 iadev->num_tx_desc = IA_TX_BUF;
784 iadev->tx_buf_sz = IA_TX_BUF_SZ;
786 iadev->num_rx_desc = IA_RX_BUF / 8;
788 iadev->num_rx_desc = IA_RX_BUF;
789 iadev->rx_buf_sz = IA_RX_BUF_SZ;
791 iadev->rx_pkt_ram = TX_PACKET_RAM + (iadev->num_tx_desc * iadev->tx_buf_sz);
793 iadev->num_tx_desc, iadev->tx_buf_sz, iadev->num_rx_desc,
794 iadev->rx_buf_sz, iadev->rx_pkt_ram);)
798 iadev->phy_type = PHY_OC3C_S;
800 iadev->phy_type = PHY_UTP155;
802 iadev->phy_type = PHY_OC3C_M;
805 iadev->phy_type = memType & FE_MASK;
807 memType,iadev->phy_type);)
808 if (iadev->phy_type == FE_25MBIT_PHY)
809 iadev->LineRate = (u32)(((25600000/8)*26)/(27*53));
810 else if (iadev->phy_type == FE_DS3_PHY)
811 iadev->LineRate = (u32)(((44736000/8)*26)/(27*53));
812 else if (iadev->phy_type == FE_E3_PHY)
813 iadev->LineRate = (u32)(((34368000/8)*26)/(27*53));
815 iadev->LineRate = (u32)(ATM_OC3_PCR);
816 IF_INIT(printk("iadev->LineRate = %d \n", iadev->LineRate);)
830 static void ia_frontend_intr(struct iadev_priv *iadev) argument
834 if (iadev->phy_type & FE_25MBIT_PHY) {
835 status = ia_phy_read32(iadev, MB25_INTR_STATUS);
836 iadev->carrier_detect = (status & MB25_IS_GSB) ? 1 : 0;
837 } else if (iadev->phy_type & FE_DS3_PHY) {
838 ia_phy_read32(iadev, SUNI_DS3_FRM_INTR_STAT);
839 status = ia_phy_read32(iadev, SUNI_DS3_FRM_STAT);
840 iadev->carrier_detect = (status & SUNI_DS3_LOSV) ? 0 : 1;
841 } else if (iadev->phy_type & FE_E3_PHY) {
842 ia_phy_read32(iadev, SUNI_E3_FRM_MAINT_INTR_IND);
843 status = ia_phy_read32(iadev, SUNI_E3_FRM_FRAM_INTR_IND_STAT);
844 iadev->carrier_detect = (status & SUNI_E3_LOS) ? 0 : 1;
846 status = ia_phy_read32(iadev, SUNI_RSOP_STATUS);
847 iadev->carrier_detect = (status & SUNI_LOSV) ? 0 : 1;
851 iadev->carrier_detect ? "detected" : "lost signal");
854 static void ia_mb25_init(struct iadev_priv *iadev) argument
859 ia_phy_write32(iadev, MB25_MASTER_CTRL, MB25_MC_DRIC | MB25_MC_DREC);
860 ia_phy_write32(iadev, MB25_DIAG_CONTROL, 0);
862 iadev->carrier_detect =
863 (ia_phy_read32(iadev, MB25_INTR_STATUS) & MB25_IS_GSB) ? 1 : 0;
871 static void ia_phy_write(struct iadev_priv *iadev, argument
875 ia_phy_write32(iadev, regs->reg, regs->val);
880 static void ia_suni_pm7345_init_ds3(struct iadev_priv *iadev) argument
892 status = ia_phy_read32(iadev, SUNI_DS3_FRM_STAT);
893 iadev->carrier_detect = (status & SUNI_DS3_LOSV) ? 0 : 1;
895 ia_phy_write(iadev, suni_ds3_init, ARRAY_SIZE(suni_ds3_init));
898 static void ia_suni_pm7345_init_e3(struct iadev_priv *iadev) argument
913 status = ia_phy_read32(iadev, SUNI_E3_FRM_FRAM_INTR_IND_STAT);
914 iadev->carrier_detect = (status & SUNI_E3_LOS) ? 0 : 1;
915 ia_phy_write(iadev, suni_e3_init, ARRAY_SIZE(suni_e3_init));
918 static void ia_suni_pm7345_init(struct iadev_priv *iadev) argument
956 if (iadev->phy_type & FE_DS3_PHY)
957 ia_suni_pm7345_init_ds3(iadev);
959 ia_suni_pm7345_init_e3(iadev);
961 ia_phy_write(iadev, suni_init, ARRAY_SIZE(suni_init));
963 ia_phy_write32(iadev, SUNI_CONFIG, ia_phy_read32(iadev, SUNI_CONFIG) &
1014 RAM_BASE*((iadev->mem)/(128 * 1024))
1016 IPHASE5575_FRAG_CONTROL_RAM_BASE*((iadev->mem)/(128 * 1024))
1018 IPHASE5575_REASS_CONTROL_RAM_BASE*((iadev->mem)/(128 * 1024))
1023 static void desc_dbg(IADEV *iadev) { argument
1029 tcq_wr_ptr = readw(iadev->seg_reg+TCQ_WR_PTR);
1031 tcq_wr_ptr, readw(iadev->seg_ram+tcq_wr_ptr),
1032 readw(iadev->seg_ram+tcq_wr_ptr-2));
1033 printk(" host_tcq_wr = 0x%x host_tcq_rd = 0x%x \n", iadev->host_tcq_wr,
1034 iadev->ffL.tcq_rd);
1035 tcq_st_ptr = readw(iadev->seg_reg+TCQ_ST_ADR);
1036 tcq_ed_ptr = readw(iadev->seg_reg+TCQ_ED_ADR);
1040 tmp = iadev->seg_ram+tcq_st_ptr;
1044 for(i=0; i <iadev->num_tx_desc; i++)
1045 printk("Desc_tbl[%d] = %d \n", i, iadev->desc_tbl[i].timestamp);
1054 IADEV *iadev;
1059 iadev = INPH_IA_DEV(dev);
1060 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1063 excpq_rd_ptr = readw(iadev->reass_reg + EXCP_Q_RD_PTR) & 0xffff;
1065 if (excpq_rd_ptr == *(u16*)(iadev->reass_reg + EXCP_Q_WR_PTR))
1068 vci = readw(iadev->reass_ram+excpq_rd_ptr);
1069 error = readw(iadev->reass_ram+excpq_rd_ptr+2) & 0x0007;
1072 if (excpq_rd_ptr > (readw(iadev->reass_reg + EXCP_Q_ED_ADR)& 0xffff))
1073 excpq_rd_ptr = readw(iadev->reass_reg + EXCP_Q_ST_ADR)& 0xffff;
1074 writew( excpq_rd_ptr, iadev->reass_reg + EXCP_Q_RD_PTR);
1075 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1082 IADEV *iadev; local
1083 iadev = INPH_IA_DEV(dev);
1084 writew(desc, iadev->reass_ram+iadev->rfL.fdq_wr);
1085 iadev->rfL.fdq_wr +=2;
1086 if (iadev->rfL.fdq_wr > iadev->rfL.fdq_ed)
1087 iadev->rfL.fdq_wr = iadev->rfL.fdq_st;
1088 writew(iadev->rfL.fdq_wr, iadev->reass_reg+FREEQ_WR_PTR);
1094 IADEV *iadev; local
1104 iadev = INPH_IA_DEV(dev);
1105 if (iadev->rfL.pcq_rd == (readw(iadev->reass_reg+PCQ_WR_PTR)&0xffff))
1111 desc = readw(iadev->reass_ram+iadev->rfL.pcq_rd) & 0x1fff;
1113 iadev->reass_ram, iadev->rfL.pcq_rd, desc);
1115 readw(iadev->reass_reg+PCQ_WR_PTR)&0xffff);)
1117 if ( iadev->rfL.pcq_rd== iadev->rfL.pcq_ed)
1118 iadev->rfL.pcq_rd = iadev->rfL.pcq_st;
1120 iadev->rfL.pcq_rd += 2;
1121 writew(iadev->rfL.pcq_rd, iadev->reass_reg+PCQ_RD_PTR);
1126 buf_desc_ptr = iadev->RX_DESC_BASE_ADDR;
1129 if (!desc || (desc > iadev->num_rx_desc) ||
1130 ((buf_desc_ptr->vc_index & 0xffff) > iadev->num_vc)) {
1135 vcc = iadev->rx_open[buf_desc_ptr->vc_index & 0xffff];
1169 if (len > iadev->rx_buf_sz) {
1170 printk("Over %d bytes sdu received, dropped!!!\n", iadev->rx_buf_sz);
1184 skb_queue_tail(&iadev->rx_dma_q, skb);
1187 wr_ptr = iadev->rx_dle_q.write;
1188 wr_ptr->sys_pkt_addr = dma_map_single(&iadev->pci->dev, skb->data,
1195 if(++wr_ptr == iadev->rx_dle_q.end)
1196 wr_ptr = iadev->rx_dle_q.start;
1197 iadev->rx_dle_q.write = wr_ptr;
1200 writel(1, iadev->dma+IPHASE5575_RX_COUNTER);
1209 IADEV *iadev; local
1213 iadev = INPH_IA_DEV(dev);
1214 status = readl(iadev->reass_reg+REASS_INTR_STATUS_REG) & 0xffff;
1224 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1229 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1231 iadev->rxing = 1;
1235 if (iadev->rxing) {
1236 iadev->rx_tmp_cnt = iadev->rx_pkt_cnt;
1237 iadev->rx_tmp_jif = jiffies;
1238 iadev->rxing = 0;
1240 else if ((time_after(jiffies, iadev->rx_tmp_jif + 50)) &&
1241 ((iadev->rx_pkt_cnt - iadev->rx_tmp_cnt) == 0)) {
1242 for (i = 1; i <= iadev->num_rx_desc; i++)
1245 writew( ~(RX_FREEQ_EMPT|RX_EXCP_RCVD),iadev->reass_reg+REASS_MASK_REG);
1246 iadev->rxing = 1;
1271 IADEV *iadev; local
1279 iadev = INPH_IA_DEV(dev);
1286 dle = iadev->rx_dle_q.read;
1287 dle_lp = readl(iadev->dma+IPHASE5575_RX_LIST_ADDR) & (sizeof(struct dle)*DLE_ENTRIES - 1);
1288 cur_dle = (struct dle*)(iadev->rx_dle_q.start + (dle_lp >> 4));
1292 skb = skb_dequeue(&iadev->rx_dma_q);
1309 dma_unmap_single(&iadev->pci->dev, iadev->rx_dle_q.write->sys_pkt_addr,
1330 if ((length > iadev->rx_buf_sz) || (length >
1350 iadev->rx_pkt_cnt++;
1353 if (++dle == iadev->rx_dle_q.end)
1354 dle = iadev->rx_dle_q.start;
1356 iadev->rx_dle_q.read = dle;
1360 if (!iadev->rxing) {
1361 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1363 state = readl(iadev->reass_reg + REASS_MASK_REG) & 0xffff;
1365 iadev->reass_reg+REASS_MASK_REG);
1366 iadev->rxing++;
1374 IADEV *iadev; local
1380 iadev = INPH_IA_DEV(vcc->dev);
1382 if (iadev->phy_type & FE_25MBIT_PHY) {
1389 vc_table = iadev->reass_ram+RX_VC_TABLE*iadev->memSize;
1400 init_abr_vc(iadev, &srv_p);
1401 ia_open_abr_vc(iadev, &srv_p, vcc, 0);
1404 reass_ptr = iadev->reass_ram+REASS_TABLE*iadev->memSize;
1409 if (iadev->rx_open[vcc->vci])
1412 iadev->rx_open[vcc->vci] = vcc;
1418 IADEV *iadev; local
1429 iadev = INPH_IA_DEV(dev);
1433 dle_addr = dma_alloc_coherent(&iadev->pci->dev, DLE_TOTAL_SIZE,
1434 &iadev->rx_dle_dma, GFP_KERNEL);
1439 iadev->rx_dle_q.start = (struct dle *)dle_addr;
1440 iadev->rx_dle_q.read = iadev->rx_dle_q.start;
1441 iadev->rx_dle_q.write = iadev->rx_dle_q.start;
1442 iadev->rx_dle_q.end = (struct dle*)((unsigned long)dle_addr+sizeof(struct dle)*DLE_ENTRIES);
1448 writel(iadev->rx_dle_dma & 0xfffff000,
1449 iadev->dma + IPHASE5575_RX_LIST_ADDR);
1451 iadev->dma+IPHASE5575_TX_LIST_ADDR,
1452 readl(iadev->dma + IPHASE5575_TX_LIST_ADDR));
1454 iadev->dma+IPHASE5575_RX_LIST_ADDR,
1455 readl(iadev->dma + IPHASE5575_RX_LIST_ADDR));)
1457 writew(0xffff, iadev->reass_reg+REASS_MASK_REG);
1458 writew(0, iadev->reass_reg+MODE_REG);
1459 writew(RESET_REASS, iadev->reass_reg+REASS_COMMAND_REG);
1475 writew(RX_DESC_BASE >> 16, iadev->reass_reg+REASS_DESC_BASE);
1477 writew(iadev->rx_buf_sz, iadev->reass_reg+BUF_SIZE);
1480 iadev->RX_DESC_BASE_ADDR = iadev->reass_ram+RX_DESC_BASE*iadev->memSize;
1481 buf_desc_ptr = iadev->RX_DESC_BASE_ADDR;
1484 rx_pkt_start = iadev->rx_pkt_ram;
1485 for(i=1; i<=iadev->num_rx_desc; i++)
1491 rx_pkt_start += iadev->rx_buf_sz;
1494 i = FREE_BUF_DESC_Q*iadev->memSize;
1495 writew(i >> 16, iadev->reass_reg+REASS_QUEUE_BASE);
1496 writew(i, iadev->reass_reg+FREEQ_ST_ADR);
1497 writew(i+iadev->num_rx_desc*sizeof(u_short),
1498 iadev->reass_reg+FREEQ_ED_ADR);
1499 writew(i, iadev->reass_reg+FREEQ_RD_PTR);
1500 writew(i+iadev->num_rx_desc*sizeof(u_short),
1501 iadev->reass_reg+FREEQ_WR_PTR);
1503 freeq_st_adr = readw(iadev->reass_reg+FREEQ_ST_ADR);
1504 freeq_start = (u_short *)(iadev->reass_ram+freeq_st_adr);
1505 for(i=1; i<=iadev->num_rx_desc; i++)
1512 i = (PKT_COMP_Q * iadev->memSize) & 0xffff;
1513 writew(i, iadev->reass_reg+PCQ_ST_ADR);
1514 writew(i+iadev->num_vc*sizeof(u_short), iadev->reass_reg+PCQ_ED_ADR);
1515 writew(i, iadev->reass_reg+PCQ_RD_PTR);
1516 writew(i, iadev->reass_reg+PCQ_WR_PTR);
1519 i = (EXCEPTION_Q * iadev->memSize) & 0xffff;
1520 writew(i, iadev->reass_reg+EXCP_Q_ST_ADR);
1522 iadev->reass_reg+EXCP_Q_ED_ADR);
1523 writew(i, iadev->reass_reg+EXCP_Q_RD_PTR);
1524 writew(i, iadev->reass_reg+EXCP_Q_WR_PTR);
1527 iadev->rfL.fdq_st = readw(iadev->reass_reg+FREEQ_ST_ADR) & 0xffff;
1528 iadev->rfL.fdq_ed = readw(iadev->reass_reg+FREEQ_ED_ADR) & 0xffff ;
1529 iadev->rfL.fdq_rd = readw(iadev->reass_reg+FREEQ_RD_PTR) & 0xffff;
1530 iadev->rfL.fdq_wr = readw(iadev->reass_reg+FREEQ_WR_PTR) & 0xffff;
1531 iadev->rfL.pcq_st = readw(iadev->reass_reg+PCQ_ST_ADR) & 0xffff;
1532 iadev->rfL.pcq_ed = readw(iadev->reass_reg+PCQ_ED_ADR) & 0xffff;
1533 iadev->rfL.pcq_rd = readw(iadev->reass_reg+PCQ_RD_PTR) & 0xffff;
1534 iadev->rfL.pcq_wr = readw(iadev->reass_reg+PCQ_WR_PTR) & 0xffff;
1537 iadev->rfL.pcq_st, iadev->rfL.pcq_ed, iadev->rfL.pcq_rd,
1538 iadev->rfL.pcq_wr);)
1548 i = REASS_TABLE * iadev->memSize;
1549 writew((i >> 3), iadev->reass_reg+REASS_TABLE_BASE);
1551 reass_table = (u16 *)(iadev->reass_ram+i);
1552 j = REASS_TABLE_SZ * iadev->memSize;
1557 while (i != iadev->num_vc) {
1561 i = RX_VC_TABLE * iadev->memSize;
1562 writew(((i>>3) & 0xfff8) | vcsize_sel, iadev->reass_reg+VC_LKUP_BASE);
1563 vc_table = (u16 *)(iadev->reass_ram+RX_VC_TABLE*iadev->memSize);
1564 j = RX_VC_TABLE_SZ * iadev->memSize;
1576 i = ABR_VC_TABLE * iadev->memSize;
1577 writew(i >> 3, iadev->reass_reg+ABR_LKUP_BASE);
1579 i = ABR_VC_TABLE * iadev->memSize;
1580 abr_vc_table = (struct abr_vc_table *)(iadev->reass_ram+i);
1581 j = REASS_TABLE_SZ * iadev->memSize;
1592 writew(0xff00, iadev->reass_reg+VP_FILTER);
1593 writew(0, iadev->reass_reg+XTRA_RM_OFFSET);
1594 writew(0x1, iadev->reass_reg+PROTOCOL_ID);
1600 writew(0xF6F8, iadev->reass_reg+PKT_TM_CNT );
1605 writew(i, iadev->reass_reg+TMOUT_RANGE);
1608 for(i=0; i<iadev->num_tx_desc;i++)
1609 iadev->desc_tbl[i].timestamp = 0;
1612 readw(iadev->reass_reg+REASS_INTR_STATUS_REG);
1615 writew(~(RX_FREEQ_EMPT|RX_PKT_RCVD), iadev->reass_reg+REASS_MASK_REG);
1617 skb_queue_head_init(&iadev->rx_dma_q);
1618 iadev->rx_free_desc_qhead = NULL;
1620 iadev->rx_open = kzalloc(4 * iadev->num_vc, GFP_KERNEL);
1621 if (!iadev->rx_open) {
1627 iadev->rxing = 1;
1628 iadev->rx_pkt_cnt = 0;
1630 writew(R_ONLINE, iadev->reass_reg+MODE_REG);
1634 dma_free_coherent(&iadev->pci->dev, DLE_TOTAL_SIZE, iadev->rx_dle_q.start,
1635 iadev->rx_dle_dma);
1658 IADEV *iadev; local
1662 iadev = INPH_IA_DEV(dev);
1664 status = readl(iadev->seg_reg+SEG_INTR_STATUS_REG);
1668 spin_lock_irqsave(&iadev->tx_lock, flags);
1669 ia_tx_poll(iadev);
1670 spin_unlock_irqrestore(&iadev->tx_lock, flags);
1671 writew(TRANSMIT_DONE, iadev->seg_reg+SEG_INTR_STATUS_REG);
1672 if (iadev->close_pending)
1673 wake_up(&iadev->close_wait);
1683 IADEV *iadev; local
1691 iadev = INPH_IA_DEV(dev);
1692 spin_lock_irqsave(&iadev->tx_lock, flags);
1693 dle = iadev->tx_dle_q.read;
1694 dle_lp = readl(iadev->dma+IPHASE5575_TX_LIST_ADDR) &
1696 cur_dle = (struct dle*)(iadev->tx_dle_q.start + (dle_lp >> 4));
1700 skb = skb_dequeue(&iadev->tx_dma_q);
1704 if (!((dle - iadev->tx_dle_q.start)%(2*sizeof(struct dle)))) {
1705 dma_unmap_single(&iadev->pci->dev, dle->sys_pkt_addr, skb->len,
1711 spin_unlock_irqrestore(&iadev->tx_lock, flags);
1719 spin_unlock_irqrestore(&iadev->tx_lock, flags);
1723 if (vcc->qos.txtp.pcr >= iadev->rate_limit) {
1737 if (++dle == iadev->tx_dle_q.end)
1738 dle = iadev->tx_dle_q.start;
1740 iadev->tx_dle_q.read = dle;
1741 spin_unlock_irqrestore(&iadev->tx_lock, flags);
1747 IADEV *iadev; local
1753 iadev = INPH_IA_DEV(vcc->dev);
1755 if (iadev->phy_type & FE_25MBIT_PHY) {
1768 (iadev->tx_buf_sz - sizeof(struct cpcs_trailer))){
1770 vcc->qos.txtp.max_sdu,iadev->tx_buf_sz);
1780 vcc->qos.txtp.pcr = iadev->LineRate;
1782 vcc->qos.txtp.pcr = iadev->LineRate;
1785 if (vcc->qos.txtp.pcr > iadev->LineRate)
1786 vcc->qos.txtp.pcr = iadev->LineRate;
1789 if (ia_vcc->pcr > (iadev->LineRate / 6) ) ia_vcc->ltimeout = HZ / 10;
1790 else if (ia_vcc->pcr > (iadev->LineRate / 130)) ia_vcc->ltimeout = HZ;
1793 if (ia_vcc->pcr < iadev->rate_limit)
1795 if (ia_vcc->pcr < iadev->rate_limit) {
1810 vc = (struct main_vc *)iadev->MAIN_VC_TABLE_ADDR;
1811 evc = (struct ext_vc *)iadev->EXT_VC_TABLE_ADDR;
1830 vc->acr = cellrate_to_float(iadev->LineRate);
1839 init_abr_vc(iadev, &srv_p);
1843 int tmpsum = iadev->sum_mcr+iadev->sum_cbr+vcc->qos.txtp.min_pcr;
1844 if (tmpsum > iadev->LineRate)
1847 iadev->sum_mcr += vcc->qos.txtp.min_pcr;
1872 ia_open_abr_vc(iadev, &srv_p, vcc, 1);
1874 if (iadev->phy_type & FE_25MBIT_PHY) {
1878 if (vcc->qos.txtp.max_pcr > iadev->LineRate) {
1884 if ((ret = ia_cbr_setup (iadev, vcc)) < 0) {
1891 iadev->testTable[vcc->vci]->vc_status |= VC_ACTIVE;
1899 IADEV *iadev; local
1913 iadev = INPH_IA_DEV(dev);
1914 spin_lock_init(&iadev->tx_lock);
1917 readw(iadev->seg_reg+SEG_MASK_REG));)
1920 dle_addr = dma_alloc_coherent(&iadev->pci->dev, DLE_TOTAL_SIZE,
1921 &iadev->tx_dle_dma, GFP_KERNEL);
1926 iadev->tx_dle_q.start = (struct dle*)dle_addr;
1927 iadev->tx_dle_q.read = iadev->tx_dle_q.start;
1928 iadev->tx_dle_q.write = iadev->tx_dle_q.start;
1929 iadev->tx_dle_q.end = (struct dle*)((unsigned long)dle_addr+sizeof(struct dle)*DLE_ENTRIES);
1932 writel(iadev->tx_dle_dma & 0xfffff000,
1933 iadev->dma + IPHASE5575_TX_LIST_ADDR);
1934 writew(0xffff, iadev->seg_reg+SEG_MASK_REG);
1935 writew(0, iadev->seg_reg+MODE_REG_0);
1936 writew(RESET_SEG, iadev->seg_reg+SEG_COMMAND_REG);
1937 iadev->MAIN_VC_TABLE_ADDR = iadev->seg_ram+MAIN_VC_TABLE*iadev->memSize;
1938 iadev->EXT_VC_TABLE_ADDR = iadev->seg_ram+EXT_VC_TABLE*iadev->memSize;
1939 iadev->ABR_SCHED_TABLE_ADDR=iadev->seg_ram+ABR_SCHED_TABLE*iadev->memSize;
1961 writew(TX_DESC_BASE, iadev->seg_reg+SEG_DESC_BASE);
1964 buf_desc_ptr =(struct tx_buf_desc *)(iadev->seg_ram+TX_DESC_BASE);
1968 for(i=1; i<=iadev->num_tx_desc; i++)
1975 tx_pkt_start += iadev->tx_buf_sz;
1977 iadev->tx_buf = kmalloc(iadev->num_tx_desc*sizeof(struct cpcs_trailer_desc), GFP_KERNEL);
1978 if (!iadev->tx_buf) {
1982 for (i= 0; i< iadev->num_tx_desc; i++)
1991 iadev->tx_buf[i].cpcs = cpcs;
1992 iadev->tx_buf[i].dma_addr = dma_map_single(&iadev->pci->dev,
1997 iadev->desc_tbl = kmalloc(iadev->num_tx_desc *
1999 if (!iadev->desc_tbl) {
2005 i = TX_COMP_Q * iadev->memSize;
2006 writew(i >> 16, iadev->seg_reg+SEG_QUEUE_BASE);
2009 writew(i, iadev->seg_reg+TCQ_ST_ADR);
2010 writew(i, iadev->seg_reg+TCQ_RD_PTR);
2011 writew(i+iadev->num_tx_desc*sizeof(u_short),iadev->seg_reg+TCQ_WR_PTR);
2012 iadev->host_tcq_wr = i + iadev->num_tx_desc*sizeof(u_short);
2013 writew(i+2 * iadev->num_tx_desc * sizeof(u_short),
2014 iadev->seg_reg+TCQ_ED_ADR);
2016 tcq_st_adr = readw(iadev->seg_reg+TCQ_ST_ADR);
2017 tcq_start = (u_short *)(iadev->seg_ram+tcq_st_adr);
2018 for(i=1; i<=iadev->num_tx_desc; i++)
2025 i = PKT_RDY_Q * iadev->memSize;
2026 writew(i, iadev->seg_reg+PRQ_ST_ADR);
2027 writew(i+2 * iadev->num_tx_desc * sizeof(u_short),
2028 iadev->seg_reg+PRQ_ED_ADR);
2029 writew(i, iadev->seg_reg+PRQ_RD_PTR);
2030 writew(i, iadev->seg_reg+PRQ_WR_PTR);
2033 iadev->ffL.prq_st = readw(iadev->seg_reg+PRQ_ST_ADR) & 0xffff;
2034 iadev->ffL.prq_ed = readw(iadev->seg_reg+PRQ_ED_ADR) & 0xffff;
2035 iadev->ffL.prq_wr = readw(iadev->seg_reg+PRQ_WR_PTR) & 0xffff;
2037 iadev->ffL.tcq_st = readw(iadev->seg_reg+TCQ_ST_ADR) & 0xffff;
2038 iadev->ffL.tcq_ed = readw(iadev->seg_reg+TCQ_ED_ADR) & 0xffff;
2039 iadev->ffL.tcq_rd = readw(iadev->seg_reg+TCQ_RD_PTR) & 0xffff;
2043 prq_st_adr = readw(iadev->seg_reg+PRQ_ST_ADR);
2044 prq_start = (u_short *)(iadev->seg_ram+prq_st_adr);
2045 for(i=1; i<=iadev->num_tx_desc; i++)
2053 writew(0,iadev->seg_reg+CBR_PTR_BASE);
2055 tmp16 = (iadev->seg_ram+CBR_SCHED_TABLE*iadev->memSize)>>17;
2057 writew(tmp16,iadev->seg_reg+CBR_PTR_BASE);
2061 readw(iadev->seg_reg+CBR_PTR_BASE));)
2062 tmp16 = (CBR_SCHED_TABLE*iadev->memSize) >> 1;
2063 writew(tmp16, iadev->seg_reg+CBR_TAB_BEG);
2065 readw(iadev->seg_reg+CBR_TAB_BEG));)
2066 writew(tmp16, iadev->seg_reg+CBR_TAB_END+1); // CBR_PTR;
2067 tmp16 = (CBR_SCHED_TABLE*iadev->memSize + iadev->num_vc*6 - 2) >> 1;
2068 writew(tmp16, iadev->seg_reg+CBR_TAB_END);
2070 iadev->seg_reg, readw(iadev->seg_reg+CBR_PTR_BASE));)
2072 readw(iadev->seg_reg+CBR_TAB_BEG), readw(iadev->seg_reg+CBR_TAB_END),
2073 readw(iadev->seg_reg+CBR_TAB_END+1));)
2076 memset_io(iadev->seg_ram+CBR_SCHED_TABLE*iadev->memSize,
2077 0, iadev->num_vc*6);
2078 iadev->CbrRemEntries = iadev->CbrTotEntries = iadev->num_vc*3;
2079 iadev->CbrEntryPt = 0;
2080 iadev->Granularity = MAX_ATM_155 / iadev->CbrTotEntries;
2081 iadev->NumEnabledCBR = 0;
2094 while (i != iadev->num_vc) {
2099 i = MAIN_VC_TABLE * iadev->memSize;
2100 writew(vcsize_sel | ((i >> 8) & 0xfff8),iadev->seg_reg+VCT_BASE);
2101 i = EXT_VC_TABLE * iadev->memSize;
2102 writew((i >> 8) & 0xfffe, iadev->seg_reg+VCTE_BASE);
2103 i = UBR_SCHED_TABLE * iadev->memSize;
2104 writew((i & 0xffff) >> 11, iadev->seg_reg+UBR_SBPTR_BASE);
2105 i = UBR_WAIT_Q * iadev->memSize;
2106 writew((i >> 7) & 0xffff, iadev->seg_reg+UBRWQ_BASE);
2107 memset((caddr_t)(iadev->seg_ram+UBR_SCHED_TABLE*iadev->memSize),
2108 0, iadev->num_vc*8);
2117 i = ABR_SCHED_TABLE * iadev->memSize;
2118 writew((i >> 11) & 0xffff, iadev->seg_reg+ABR_SBPTR_BASE);
2119 i = ABR_WAIT_Q * iadev->memSize;
2120 writew((i >> 7) & 0xffff, iadev->seg_reg+ABRWQ_BASE);
2122 i = ABR_SCHED_TABLE*iadev->memSize;
2123 memset((caddr_t)(iadev->seg_ram+i), 0, iadev->num_vc*4);
2124 vc = (struct main_vc *)iadev->MAIN_VC_TABLE_ADDR;
2125 evc = (struct ext_vc *)iadev->EXT_VC_TABLE_ADDR;
2126 iadev->testTable = kmalloc(sizeof(long)*iadev->num_vc, GFP_KERNEL);
2127 if (!iadev->testTable) {
2131 for(i=0; i<iadev->num_vc; i++)
2135 iadev->testTable[i] = kmalloc(sizeof(struct testTable_t),
2137 if (!iadev->testTable[i])
2139 iadev->testTable[i]->lastTime = 0;
2140 iadev->testTable[i]->fract = 0;
2141 iadev->testTable[i]->vc_status = VC_UBR;
2149 if (iadev->phy_type & FE_25MBIT_PHY) {
2150 writew(RATE25, iadev->seg_reg+MAXRATE);
2151 writew((UBR_EN | (0x23 << 2)), iadev->seg_reg+STPARMS);
2154 writew(cellrate_to_float(iadev->LineRate),iadev->seg_reg+MAXRATE);
2155 writew((UBR_EN | ABR_EN | (0x23 << 2)), iadev->seg_reg+STPARMS);
2158 writew(0, iadev->seg_reg+IDLEHEADHI);
2159 writew(0, iadev->seg_reg+IDLEHEADLO);
2162 writew(0xaa00, iadev->seg_reg+ABRUBR_ARB);
2164 iadev->close_pending = 0;
2165 init_waitqueue_head(&iadev->close_wait);
2166 init_waitqueue_head(&iadev->timeout_wait);
2167 skb_queue_head_init(&iadev->tx_dma_q);
2168 ia_init_rtn_q(&iadev->tx_return_q);
2171 writew(RM_TYPE_4_0, iadev->seg_reg+RM_TYPE);
2172 skb_queue_head_init (&iadev->tx_backlog);
2175 writew(MODE_REG_1_VAL, iadev->seg_reg+MODE_REG_1);
2178 writew(T_ONLINE, iadev->seg_reg+MODE_REG_0);
2181 readw(iadev->seg_reg+SEG_INTR_STATUS_REG);
2184 writew(~(TRANSMIT_DONE | TCQ_NOT_EMPTY), iadev->seg_reg+SEG_MASK_REG);
2185 writew(TRANSMIT_DONE, iadev->seg_reg+SEG_INTR_STATUS_REG);
2186 iadev->tx_pkt_cnt = 0;
2187 iadev->rate_limit = iadev->LineRate / 3;
2193 kfree(iadev->testTable[i]);
2194 kfree(iadev->testTable);
2196 kfree(iadev->desc_tbl);
2198 i = iadev->num_tx_desc;
2201 struct cpcs_trailer_desc *desc = iadev->tx_buf + i;
2203 dma_unmap_single(&iadev->pci->dev, desc->dma_addr,
2207 kfree(iadev->tx_buf);
2209 dma_free_coherent(&iadev->pci->dev, DLE_TOTAL_SIZE, iadev->tx_dle_q.start,
2210 iadev->tx_dle_dma);
2218 IADEV *iadev; local
2223 iadev = INPH_IA_DEV(dev);
2224 while( (status = readl(iadev->reg+IPHASE5575_BUS_STATUS_REG) & 0x7f))
2237 writel(STAT_DLERINT, iadev->reg + IPHASE5575_BUS_STATUS_REG);
2248 writel(STAT_DLETINT, iadev->reg + IPHASE5575_BUS_STATUS_REG);
2254 ia_frontend_intr(iadev);
2265 IADEV *iadev; local
2270 iadev = INPH_IA_DEV(dev);
2272 iadev->reg+IPHASE5575_MAC1)));
2273 mac2 = cpu_to_be16(le16_to_cpu(readl(iadev->reg+IPHASE5575_MAC2)));
2285 IADEV *iadev; local
2289 iadev = INPH_IA_DEV(dev);
2291 if ((error = pci_read_config_dword(iadev->pci,
2294 writel(0, iadev->reg+IPHASE5575_EXT_RESET);
2296 if ((error = pci_write_config_dword(iadev->pci,
2306 IADEV *iadev; local
2320 iadev = INPH_IA_DEV(dev);
2321 real_base = pci_resource_start (iadev->pci, 0);
2322 iadev->irq = iadev->pci->irq;
2324 error = pci_read_config_word(iadev->pci, PCI_COMMAND, &command);
2331 dev->number, iadev->pci->revision, real_base, iadev->irq);)
2335 iadev->pci_map_size = pci_resource_len(iadev->pci, 0);
2337 if (iadev->pci_map_size == 0x100000){
2338 iadev->num_vc = 4096;
2340 iadev->memSize = 4;
2342 else if (iadev->pci_map_size == 0x40000) {
2343 iadev->num_vc = 1024;
2344 iadev->memSize = 1;
2347 printk("Unknown pci_map_size = 0x%x\n", iadev->pci_map_size);
2350 IF_INIT(printk (DEV_LABEL "map size: %i\n", iadev->pci_map_size);)
2353 pci_set_master(iadev->pci);
2361 base = ioremap(real_base,iadev->pci_map_size); /* ioremap is not resolved ??? */
2370 dev->number, iadev->pci->revision, base, iadev->irq);)
2373 iadev->mem = iadev->pci_map_size /2;
2374 iadev->real_base = real_base;
2375 iadev->base = base;
2378 iadev->reg = base + REG_BASE;
2380 iadev->seg_reg = base + SEG_BASE;
2382 iadev->reass_reg = base + REASS_BASE;
2384 iadev->phy = base + PHY_BASE;
2385 iadev->dma = base + PHY_BASE;
2387 iadev->ram = base + ACTUAL_RAM_BASE;
2388 iadev->seg_ram = base + ACTUAL_SEG_RAM_BASE;
2389 iadev->reass_ram = base + ACTUAL_REASS_RAM_BASE;
2393 iadev->reg,iadev->seg_reg,iadev->reass_reg,
2394 iadev->phy, iadev->ram, iadev->seg_ram,
2395 iadev->reass_ram);)
2400 iounmap(iadev->base);
2410 iounmap(iadev->base);
2417 static void ia_update_stats(IADEV *iadev) { argument
2418 if (!iadev->carrier_detect)
2420 iadev->rx_cell_cnt += readw(iadev->reass_reg+CELL_CTR0)&0xffff;
2421 iadev->rx_cell_cnt += (readw(iadev->reass_reg+CELL_CTR1) & 0xffff) << 16;
2422 iadev->drop_rxpkt += readw(iadev->reass_reg + DRP_PKT_CNTR ) & 0xffff;
2423 iadev->drop_rxcell += readw(iadev->reass_reg + ERR_CNTR) & 0xffff;
2424 iadev->tx_cell_cnt += readw(iadev->seg_reg + CELL_CTR_LO_AUTO)&0xffff;
2425 iadev->tx_cell_cnt += (readw(iadev->seg_reg+CELL_CTR_HIGH_AUTO)&0xffff)<<16;
2470 static void ia_free_tx(IADEV *iadev) argument
2474 kfree(iadev->desc_tbl);
2475 for (i = 0; i < iadev->num_vc; i++)
2476 kfree(iadev->testTable[i]);
2477 kfree(iadev->testTable);
2478 for (i = 0; i < iadev->num_tx_desc; i++) {
2479 struct cpcs_trailer_desc *desc = iadev->tx_buf + i;
2481 dma_unmap_single(&iadev->pci->dev, desc->dma_addr,
2485 kfree(iadev->tx_buf);
2486 dma_free_coherent(&iadev->pci->dev, DLE_TOTAL_SIZE, iadev->tx_dle_q.start,
2487 iadev->tx_dle_dma);
2490 static void ia_free_rx(IADEV *iadev) argument
2492 kfree(iadev->rx_open);
2493 dma_free_coherent(&iadev->pci->dev, DLE_TOTAL_SIZE, iadev->rx_dle_q.start,
2494 iadev->rx_dle_dma);
2499 IADEV *iadev; local
2504 iadev = INPH_IA_DEV(dev);
2505 if (request_irq(iadev->irq, &ia_int, IRQF_SHARED, DEV_LABEL, dev)) {
2507 dev->number, iadev->irq);
2513 if ((error = pci_write_config_word(iadev->pci,
2528 readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG));)
2529 ctrl_reg = readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG);
2545 writel(ctrl_reg, iadev->reg+IPHASE5575_BUS_CONTROL_REG);
2548 readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG));
2550 readl(iadev->reg+IPHASE5575_BUS_STATUS_REG));)
2552 ia_hw_type(iadev);
2560 ctrl_reg = readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG);
2561 writel(ctrl_reg | CTRL_FE_RST, iadev->reg+IPHASE5575_BUS_CONTROL_REG);
2563 readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG));)
2571 if (iadev->phy_type & FE_25MBIT_PHY)
2572 ia_mb25_init(iadev);
2573 else if (iadev->phy_type & (FE_DS3_PHY | FE_E3_PHY))
2574 ia_suni_pm7345_init(iadev);
2585 ia_frontend_intr(iadev);
2590 ia_free_rx(iadev);
2592 ia_free_tx(iadev);
2594 free_irq(iadev->irq, dev);
2603 IADEV *iadev; local
2609 iadev = INPH_IA_DEV(vcc->dev);
2619 iadev->close_pending++;
2620 prepare_to_wait(&iadev->timeout_wait, &wait, TASK_UNINTERRUPTIBLE);
2622 finish_wait(&iadev->timeout_wait, &wait);
2623 spin_lock_irqsave(&iadev->tx_lock, flags);
2624 while((skb = skb_dequeue(&iadev->tx_backlog))) {
2633 skb_queue_tail(&iadev->tx_backlog, skb);
2638 spin_unlock_irqrestore(&iadev->tx_lock, flags);
2639 wait_event_timeout(iadev->close_wait, (ia_vcc->vc_desc_cnt <= 0), closetime);
2640 spin_lock_irqsave(&iadev->tx_lock, flags);
2641 iadev->close_pending--;
2642 iadev->testTable[vcc->vci]->lastTime = 0;
2643 iadev->testTable[vcc->vci]->fract = 0;
2644 iadev->testTable[vcc->vci]->vc_status = VC_UBR;
2647 iadev->sum_mcr -= vcc->qos.txtp.min_pcr;
2651 iadev->sum_mcr -= ia_vcc->NumCbrEntry*iadev->Granularity;
2654 spin_unlock_irqrestore(&iadev->tx_lock, flags);
2659 vc_table = (u16 *)(iadev->reass_ram+REASS_TABLE*iadev->memSize);
2663 vc_table = (u16 *)(iadev->reass_ram+RX_VC_TABLE*iadev->memSize);
2668 (iadev->reass_ram+ABR_VC_TABLE*iadev->memSize);
2675 iadev->rx_open[vcc->vci] = NULL;
2747 IADEV *iadev; local
2759 iadev = ia_dev[board];
2766 if (copy_to_user(ia_cmds.buf, iadev, sizeof(IADEV)))
2774 if(put_user((u16)(readl(iadev->seg_reg+i) & 0xffff), tmps)) return -EFAULT;
2782 if(put_user((u16)(readl(iadev->reass_reg+i) & 0xffff), tmps)) return -EFAULT;
2799 ((u_int *)rfL)[i] = readl(iadev->reass_reg + i) & 0xffff;
2802 ((u_int *)ffL)[i] = readl(iadev->seg_reg + i) & 0xffff;
2816 desc_dbg(iadev);
2823 printk("skb = 0x%lx\n", (long)skb_peek(&iadev->tx_backlog));
2824 printk("rtn_q: 0x%lx\n",(long)ia_deque_rtn_q(&iadev->tx_return_q));
2845 for (i = 1; i <= iadev->num_rx_desc; i++)
2848 iadev->reass_reg+REASS_MASK_REG);
2849 iadev->rxing = 1;
2856 ia_frontend_intr(iadev);
2894 IADEV *iadev; local
2903 iadev = INPH_IA_DEV(vcc->dev);
2914 if (skb->len > iadev->tx_buf_sz - 8) {
2935 desc = get_desc (iadev, iavcc);
2941 if ((desc == 0) || (desc > iadev->num_tx_desc))
2960 iadev->desc_tbl[desc-1].iavcc = iavcc;
2961 iadev->desc_tbl[desc-1].txskb = skb;
2964 iadev->ffL.tcq_rd += 2;
2965 if (iadev->ffL.tcq_rd > iadev->ffL.tcq_ed)
2966 iadev->ffL.tcq_rd = iadev->ffL.tcq_st;
2967 writew(iadev->ffL.tcq_rd, iadev->seg_reg+TCQ_RD_PTR);
2972 *(u16*)(iadev->seg_ram+iadev->ffL.prq_wr) = desc;
2974 iadev->ffL.prq_wr += 2;
2975 if (iadev->ffL.prq_wr > iadev->ffL.prq_ed)
2976 iadev->ffL.prq_wr = iadev->ffL.prq_st;
2985 trailer = iadev->tx_buf[desc-1].cpcs;
3000 buf_desc_ptr = iadev->seg_ram+TX_DESC_BASE;
3004 writew(TRANSMIT_DONE, iadev->seg_reg+SEG_INTR_STATUS_REG);
3009 clear_lockup (vcc, iadev);
3012 wr_ptr = iadev->tx_dle_q.write;
3014 wr_ptr->sys_pkt_addr = dma_map_single(&iadev->pci->dev, skb->data,
3029 if (++wr_ptr == iadev->tx_dle_q.end)
3030 wr_ptr = iadev->tx_dle_q.start;
3033 wr_ptr->sys_pkt_addr = iadev->tx_buf[desc-1].dma_addr;
3039 wr_ptr->prq_wr_ptr_data = iadev->ffL.prq_wr;
3042 if (++wr_ptr == iadev->tx_dle_q.end)
3043 wr_ptr = iadev->tx_dle_q.start;
3045 iadev->tx_dle_q.write = wr_ptr;
3047 skb_queue_tail(&iadev->tx_dma_q, skb);
3050 iadev->tx_pkt_cnt++;
3052 writel(2, iadev->dma+IPHASE5575_TX_COUNTER);
3075 IADEV *iadev; local
3078 iadev = INPH_IA_DEV(vcc->dev);
3079 if ((!skb)||(skb->len>(iadev->tx_buf_sz-sizeof(struct cpcs_trailer))))
3086 spin_lock_irqsave(&iadev->tx_lock, flags);
3089 spin_unlock_irqrestore(&iadev->tx_lock, flags);
3094 if (skb_peek(&iadev->tx_backlog)) {
3095 skb_queue_tail(&iadev->tx_backlog, skb);
3099 skb_queue_tail(&iadev->tx_backlog, skb);
3102 spin_unlock_irqrestore(&iadev->tx_lock, flags);
3111 IADEV *iadev = INPH_IA_DEV(dev); local
3113 if (iadev->phy_type == FE_25MBIT_PHY) {
3117 if (iadev->phy_type == FE_DS3_PHY)
3119 else if (iadev->phy_type == FE_E3_PHY)
3121 else if (iadev->phy_type == FE_UTP_OPTION)
3126 if (iadev->pci_map_size == 0x40000)
3131 if ((iadev->memType & MEM_SIZE_MASK) == MEM_SIZE_1M)
3133 else if ((iadev->memType & MEM_SIZE_MASK) == MEM_SIZE_512K)
3150 iadev->num_tx_desc, iadev->tx_buf_sz,
3151 iadev->num_rx_desc, iadev->rx_buf_sz,
3152 iadev->rx_pkt_cnt, iadev->tx_pkt_cnt,
3153 iadev->rx_cell_cnt, iadev->tx_cell_cnt,
3154 iadev->drop_rxcell, iadev->drop_rxpkt);
3176 IADEV *iadev; local
3179 iadev = kzalloc(sizeof(*iadev), GFP_KERNEL);
3180 if (!iadev) {
3185 iadev->pci = pdev;
3198 dev->dev_data = iadev;
3201 iadev->LineRate);)
3205 ia_dev[iadev_count] = iadev;
3218 iadev->next_board = ia_boards;
3228 kfree(iadev);
3236 IADEV *iadev = INPH_IA_DEV(dev); local
3247 free_irq(iadev->irq, dev);
3254 iounmap(iadev->base);
3257 ia_free_rx(iadev);
3258 ia_free_tx(iadev);
3260 kfree(iadev);