Lines Matching refs:sil_port
246 } sil_port[] = { variable
271 void __iomem *bmdma2 = mmio_base + sil_port[ap->port_no].bmdma2; in sil_bmdma_stop()
297 void __iomem *bmdma2 = mmio_base + sil_port[ap->port_no].bmdma2; in sil_bmdma_start()
364 void __iomem *addr = mmio_base + sil_port[ap->port_no].xfer_mode; in sil_set_mode()
532 u32 bmdma2 = readl(mmio_base + sil_port[ap->port_no].bmdma2); in sil_interrupt()
557 writel(0, mmio_base + sil_port[ap->port_no].sien); in sil_freeze()
590 writel(SIL_SIEN_N, mmio_base + sil_port[ap->port_no].sien); in sil_thaw()
677 mmio_base + sil_port[i].fifo_cfg); in sil_init_controller()
687 tmp = readl(mmio_base + sil_port[i].sfis_cfg); in sil_init_controller()
693 writel(tmp & ~0x3, mmio_base + sil_port[i].sfis_cfg); in sil_init_controller()
700 tmp = readl(mmio_base + sil_port[2].bmdma); in sil_init_controller()
703 mmio_base + sil_port[2].bmdma); in sil_init_controller()
786 ioaddr->cmd_addr = mmio_base + sil_port[i].tf; in sil_init_one()
788 ioaddr->ctl_addr = mmio_base + sil_port[i].ctl; in sil_init_one()
789 ioaddr->bmdma_addr = mmio_base + sil_port[i].bmdma; in sil_init_one()
790 ioaddr->scr_addr = mmio_base + sil_port[i].scr; in sil_init_one()
794 ata_port_pbar_desc(ap, SIL_MMIO_BAR, sil_port[i].tf, "tf"); in sil_init_one()