3171 #undef ZERO
3172 #define ZERO(reg) writel(0, port_mmio + (reg))  macro
3180 	ZERO(0x028);	/* command */  in mv5_reset_hc_port()
3182 	ZERO(0x004);	/* timer */  in mv5_reset_hc_port()
3183 	ZERO(0x008);	/* irq err cause */  in mv5_reset_hc_port()
3184 	ZERO(0x00c);	/* irq err mask */  in mv5_reset_hc_port()
3185 	ZERO(0x010);	/* rq bah */  in mv5_reset_hc_port()
3186 	ZERO(0x014);	/* rq inp */  in mv5_reset_hc_port()
3187 	ZERO(0x018);	/* rq outp */  in mv5_reset_hc_port()
3188 	ZERO(0x01c);	/* respq bah */  in mv5_reset_hc_port()
3189 	ZERO(0x024);	/* respq outp */  in mv5_reset_hc_port()
3190 	ZERO(0x020);	/* respq inp */  in mv5_reset_hc_port()
3191 	ZERO(0x02c);	/* test control */  in mv5_reset_hc_port()
3194 #undef ZERO
3196 #define ZERO(reg) writel(0, hc_mmio + (reg))  macro
3203 	ZERO(0x00c);  in mv5_reset_one_hc()
3204 	ZERO(0x010);  in mv5_reset_one_hc()
3205 	ZERO(0x014);  in mv5_reset_one_hc()
3206 	ZERO(0x018);  in mv5_reset_one_hc()
3213 #undef ZERO
3231 #undef ZERO
3232 #define ZERO(reg) writel(0, mmio + (reg))  macro
3242 	ZERO(MV_PCI_DISC_TIMER);  in mv_reset_pci_bus()
3243 	ZERO(MV_PCI_MSI_TRIGGER);  in mv_reset_pci_bus()
3245 	ZERO(MV_PCI_SERR_MASK);  in mv_reset_pci_bus()
3246 	ZERO(hpriv->irq_cause_offset);  in mv_reset_pci_bus()
3247 	ZERO(hpriv->irq_mask_offset);  in mv_reset_pci_bus()
3248 	ZERO(MV_PCI_ERR_LOW_ADDRESS);  in mv_reset_pci_bus()
3249 	ZERO(MV_PCI_ERR_HIGH_ADDRESS);  in mv_reset_pci_bus()
3250 	ZERO(MV_PCI_ERR_ATTRIBUTE);  in mv_reset_pci_bus()
3251 	ZERO(MV_PCI_ERR_COMMAND);  in mv_reset_pci_bus()
3253 #undef ZERO
3453 #undef ZERO
3454 #define ZERO(reg) writel(0, port_mmio + (reg))  macro
3462 	ZERO(0x028);		/* command */  in mv_soc_reset_hc_port()
3464 	ZERO(0x004);		/* timer */  in mv_soc_reset_hc_port()
3465 	ZERO(0x008);		/* irq err cause */  in mv_soc_reset_hc_port()
3466 	ZERO(0x00c);		/* irq err mask */  in mv_soc_reset_hc_port()
3467 	ZERO(0x010);		/* rq bah */  in mv_soc_reset_hc_port()
3468 	ZERO(0x014);		/* rq inp */  in mv_soc_reset_hc_port()
3469 	ZERO(0x018);		/* rq outp */  in mv_soc_reset_hc_port()
3470 	ZERO(0x01c);		/* respq bah */  in mv_soc_reset_hc_port()
3471 	ZERO(0x024);		/* respq outp */  in mv_soc_reset_hc_port()
3472 	ZERO(0x020);		/* respq inp */  in mv_soc_reset_hc_port()
3473 	ZERO(0x02c);		/* test control */  in mv_soc_reset_hc_port()
3477 #undef ZERO
3479 #define ZERO(reg) writel(0, hc_mmio + (reg))  macro
3485 	ZERO(0x00c);  in mv_soc_reset_one_hc()
3486 	ZERO(0x010);  in mv_soc_reset_one_hc()
3487 	ZERO(0x014);  in mv_soc_reset_one_hc()
3491 #undef ZERO