Lines Matching refs:mmio_base
235 void __iomem *mmio_base; member
262 return hpriv->mmio_base + ap->port_no * PORT_SIZE; in inic_port_base()
420 host_irq_stat = readw(hpriv->mmio_base + HOST_IRQ_STAT); in inic_interrupt()
748 static int init_controller(void __iomem *mmio_base, u16 hctl) in init_controller() argument
758 writew(hctl | HCTL_SOFTRST, mmio_base + HOST_CTL); in init_controller()
759 readw(mmio_base + HOST_CTL); /* flush */ in init_controller()
763 val = readw(mmio_base + HOST_CTL); in init_controller()
773 void __iomem *port_base = mmio_base + i * PORT_SIZE; in init_controller()
780 writew(hctl & ~HCTL_IRQOFF, mmio_base + HOST_CTL); in init_controller()
781 val = readw(mmio_base + HOST_IRQ_MASK); in init_controller()
783 writew(val, mmio_base + HOST_IRQ_MASK); in init_controller()
800 rc = init_controller(hpriv->mmio_base, hpriv->cached_hctl); in inic_pci_device_resume()
848 hpriv->mmio_base = iomap[mmio_bar]; in inic_init_one()
849 hpriv->cached_hctl = readw(hpriv->mmio_base + HOST_CTL); in inic_init_one()
882 rc = init_controller(hpriv->mmio_base, hpriv->cached_hctl); in inic_init_one()