Lines Matching refs:addr

138 #define flush_cache_page(vma, addr, pfn)		do { } while (0)  argument
189 static inline u32 xtensa_get_dtlb1(u32 addr) in xtensa_get_dtlb1() argument
191 u32 r = addr & XTENSA_CACHEBLK_MASK; in xtensa_get_dtlb1()
196 static inline u32 xtensa_get_dtlb1(u32 addr) in xtensa_get_dtlb1() argument
199 asm volatile(" rdtlb1 %0, %1" : "=a"(r) : "a"(addr)); in xtensa_get_dtlb1()
216 static inline int xtensa_need_flush_dma_source(u32 addr) in xtensa_need_flush_dma_source() argument
218 return (xtensa_get_dtlb1(addr) & ((1 << XCHAL_CA_BITS) - 1)) >= 4; in xtensa_need_flush_dma_source()
221 static inline int xtensa_need_invalidate_dma_destination(u32 addr) in xtensa_need_invalidate_dma_destination() argument
223 return (xtensa_get_dtlb1(addr) & ((1 << XCHAL_CA_BITS) - 1)) != 2; in xtensa_need_invalidate_dma_destination()
226 static inline void flush_dcache_unaligned(u32 addr, u32 size) in flush_dcache_unaligned() argument
230 cnt = (size + ((XCHAL_DCACHE_LINESIZE - 1) & addr) in flush_dcache_unaligned()
233 asm volatile(" dhwb %0, 0" : : "a"(addr)); in flush_dcache_unaligned()
234 addr += XCHAL_DCACHE_LINESIZE; in flush_dcache_unaligned()
240 static inline void invalidate_dcache_unaligned(u32 addr, u32 size) in invalidate_dcache_unaligned() argument
244 asm volatile(" dhwbi %0, 0 ;" : : "a"(addr)); in invalidate_dcache_unaligned()
245 cnt = (size + ((XCHAL_DCACHE_LINESIZE - 1) & addr) in invalidate_dcache_unaligned()
248 asm volatile(" dhi %0, %1" : : "a"(addr), in invalidate_dcache_unaligned()
250 addr += XCHAL_DCACHE_LINESIZE; in invalidate_dcache_unaligned()
252 asm volatile(" dhwbi %0, %1" : : "a"(addr), in invalidate_dcache_unaligned()
258 static inline void flush_invalidate_dcache_unaligned(u32 addr, u32 size) in flush_invalidate_dcache_unaligned() argument
262 cnt = (size + ((XCHAL_DCACHE_LINESIZE - 1) & addr) in flush_invalidate_dcache_unaligned()
265 asm volatile(" dhwbi %0, 0" : : "a"(addr)); in flush_invalidate_dcache_unaligned()
266 addr += XCHAL_DCACHE_LINESIZE; in flush_invalidate_dcache_unaligned()