12 static void pci_fixup_i450nx(struct pci_dev *d)  in pci_fixup_i450nx()  argument
20 	dev_warn(&d->dev, "Searching for i450NX host bridges\n");  in pci_fixup_i450nx()
23 		pci_read_config_byte(d, reg++, &busno);  in pci_fixup_i450nx()
24 		pci_read_config_byte(d, reg++, &suba);  in pci_fixup_i450nx()
25 		pci_read_config_byte(d, reg++, &subb);  in pci_fixup_i450nx()
26 		dev_dbg(&d->dev, "i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno,  in pci_fixup_i450nx()
37 static void pci_fixup_i450gx(struct pci_dev *d)  in pci_fixup_i450gx()  argument
44 	pci_read_config_byte(d, 0x4a, &busno);  in pci_fixup_i450gx()
45 	dev_info(&d->dev, "i440KX/GX host bridge; secondary bus %02x\n", busno);  in pci_fixup_i450gx()
51 static void pci_fixup_umc_ide(struct pci_dev *d)  in pci_fixup_umc_ide()  argument
59 	dev_warn(&d->dev, "Fixing base address flags\n");  in pci_fixup_umc_ide()
61 		d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO;  in pci_fixup_umc_ide()
65 static void pci_fixup_ncr53c810(struct pci_dev *d)  in pci_fixup_ncr53c810()  argument
71 	if (!d->class) {  in pci_fixup_ncr53c810()
72 		dev_warn(&d->dev, "Fixing NCR 53C810 class code\n");  in pci_fixup_ncr53c810()
73 		d->class = PCI_CLASS_STORAGE_SCSI << 8;  in pci_fixup_ncr53c810()
78 static void pci_fixup_latency(struct pci_dev *d)  in pci_fixup_latency()  argument
84 	dev_dbg(&d->dev, "Setting max latency to 32\n");  in pci_fixup_latency()
90 static void pci_fixup_piix4_acpi(struct pci_dev *d)  in pci_fixup_piix4_acpi()  argument
95 	d->irq = 9;  in pci_fixup_piix4_acpi()
119 static void pci_fixup_via_northbridge_bug(struct pci_dev *d)  in pci_fixup_via_northbridge_bug()  argument
125 	if (d->device == PCI_DEVICE_ID_VIA_8367_0) {  in pci_fixup_via_northbridge_bug()
129 		pci_write_config_byte(d, PCI_LATENCY_TIMER, 0);  in pci_fixup_via_northbridge_bug()
133 	} else if (d->device == PCI_DEVICE_ID_VIA_8363_0 &&  in pci_fixup_via_northbridge_bug()
134 			(d->revision == VIA_8363_KL133_REVISION_ID ||  in pci_fixup_via_northbridge_bug()
135 			d->revision == VIA_8363_KM133_REVISION_ID)) {  in pci_fixup_via_northbridge_bug()
140 	pci_read_config_byte(d, where, &v);  in pci_fixup_via_northbridge_bug()
142 …dev_warn(&d->dev, "Disabling VIA memory write queue (PCI ID %04x, rev %02x): [%02x] %02x & %02x ->…  in pci_fixup_via_northbridge_bug()
143 			d->device, d->revision, where, v, mask, v & mask);  in pci_fixup_via_northbridge_bug()
145 		pci_write_config_byte(d, where, v);  in pci_fixup_via_northbridge_bug()