78 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)  in apic_set_reg()  function
219 	apic_set_reg(apic, APIC_SPIV, val);  in apic_set_spiv()
233 	apic_set_reg(apic, APIC_ID, id << 24);  in kvm_apic_set_id()
239 	apic_set_reg(apic, APIC_LDR, id);  in kvm_apic_set_ldr()
285 	apic_set_reg(apic, APIC_LVR, v);  in kvm_apic_set_version()
553 		apic_set_reg(apic, APIC_TMR + 0x10 * i, tmr[i]);  in kvm_apic_update_tmr()
575 		apic_set_reg(apic, APIC_PROCPRI, ppr);  in apic_update_ppr()
583 	apic_set_reg(apic, APIC_TASKPRI, tpr);  in apic_set_tpr()
1293 			apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);  in apic_reg_write()
1311 				apic_set_reg(apic, APIC_LVTT + 0x10 * i,  in apic_reg_write()
1322 		apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));  in apic_reg_write()
1329 		apic_set_reg(apic, APIC_ICR2, val);  in apic_reg_write()
1343 		apic_set_reg(apic, reg, val);  in apic_reg_write()
1351 		apic_set_reg(apic, APIC_LVTT, val);  in apic_reg_write()
1360 		apic_set_reg(apic, APIC_TMICT, val);  in apic_reg_write()
1367 		apic_set_reg(apic, APIC_TDCR, val);  in apic_reg_write()
1585 		apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);  in kvm_lapic_reset()
1587 	apic_set_reg(apic, APIC_LVT0,  in kvm_lapic_reset()
1590 	apic_set_reg(apic, APIC_DFR, 0xffffffffU);  in kvm_lapic_reset()
1592 	apic_set_reg(apic, APIC_TASKPRI, 0);  in kvm_lapic_reset()
1594 	apic_set_reg(apic, APIC_ESR, 0);  in kvm_lapic_reset()
1595 	apic_set_reg(apic, APIC_ICR, 0);  in kvm_lapic_reset()
1596 	apic_set_reg(apic, APIC_ICR2, 0);  in kvm_lapic_reset()
1597 	apic_set_reg(apic, APIC_TDCR, 0);  in kvm_lapic_reset()
1598 	apic_set_reg(apic, APIC_TMICT, 0);  in kvm_lapic_reset()
1600 		apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);  in kvm_lapic_reset()
1601 		apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);  in kvm_lapic_reset()
1602 		apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);  in kvm_lapic_reset()