Lines Matching defs:cpu_hw_events
163 struct cpu_hw_events { struct
167 struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */
168 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
169 unsigned long running[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
170 int enabled;
172 int n_events; /* the # of events in the below arrays */
173 int n_added; /* the # last events in the below arrays;
175 int n_txn; /* the # last events in the below arrays;
177 int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
178 u64 tags[X86_PMC_IDX_MAX];
180 struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
181 struct event_constraint *event_constraint[X86_PMC_IDX_MAX];
183 int n_excl; /* the number of exclusive events */
185 unsigned int group_flag;
186 int is_fake;
191 struct debug_store *ds;
192 u64 pebs_enabled;
197 int lbr_users;
198 void *lbr_context;
199 struct perf_branch_stack lbr_stack;
200 struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES];
201 struct er_account *lbr_sel;
202 u64 br_sel;
207 u64 intel_ctrl_guest_mask;
208 u64 intel_ctrl_host_mask;
209 struct perf_guest_switch_msr guest_switch_msrs[X86_PMC_IDX_MAX];
214 u64 intel_cp_status;
220 struct intel_shared_regs *shared_regs;
224 struct event_constraint *constraint_list; /* in enable order */
225 struct intel_excl_cntrs *excl_cntrs;
226 int excl_thread_id; /* 0 or 1 */
231 struct amd_nb *amd_nb;
233 u64 perf_ctr_virt_mask;
235 void *kfree_on_online[X86_PERF_KFREE_MAX];