84 	switch (b->address) {  in bank4_names()
96 		WARN(1, "Funny MSR: 0x%08x\n", b->address);  in bank4_names()
124 		       b->bank, b->block, b->address, hi, lo);  in lvt_off_valid()
131 		       b->cpu, apic, b->bank, b->block, b->address, hi, lo);  in lvt_off_valid()
147 	rdmsr(tr->b->address, lo, hi);  in threshold_restart_bank()
184 	wrmsr(tr->b->address, lo, hi);  in threshold_restart_bank()
213 	u32 low = 0, high = 0, address = 0;  in mce_amd_feature_init()  local
220 				address = MSR_IA32_MCx_MISC(bank);  in mce_amd_feature_init()
222 				address = (low & MASK_BLKPTR_LO) >> 21;  in mce_amd_feature_init()
223 				if (!address)  in mce_amd_feature_init()
226 				address += MCG_XBLK_ADDR;  in mce_amd_feature_init()
228 				++address;  in mce_amd_feature_init()
230 			if (rdmsr_safe(address, &low, &high))  in mce_amd_feature_init()
247 			b.address		= address;  in mce_amd_feature_init()
278 	u32 low = 0, high = 0, address = 0;  in amd_threshold_interrupt()  local
289 				address = MSR_IA32_MCx_MISC(bank);  in amd_threshold_interrupt()
291 				address = (low & MASK_BLKPTR_LO) >> 21;  in amd_threshold_interrupt()
292 				if (!address)  in amd_threshold_interrupt()
294 				address += MCG_XBLK_ADDR;  in amd_threshold_interrupt()
296 				++address;  in amd_threshold_interrupt()
299 			if (rdmsr_safe(address, &low, &high))  in amd_threshold_interrupt()
403 	rdmsr_on_cpu(b->cpu, b->address, &lo, &hi);  in show_error_count()
468 				     unsigned int block, u32 address)  in allocate_threshold_blocks()  argument
477 	if (rdmsr_safe_on_cpu(cpu, address, &low, &high))  in allocate_threshold_blocks()
498 	b->address		= address;  in allocate_threshold_blocks()
526 		address = (low & MASK_BLKPTR_LO) >> 21;  in allocate_threshold_blocks()
527 		if (!address)  in allocate_threshold_blocks()
529 		address += MCG_XBLK_ADDR;  in allocate_threshold_blocks()
531 		++address;  in allocate_threshold_blocks()
534 	err = allocate_threshold_blocks(cpu, bank, ++block, address);  in allocate_threshold_blocks()