Lines Matching refs:REG2
98 #define TSB_CAS_TAG_HIGH(TSB, REG1, REG2) \ argument
99 661: casa [TSB] ASI_N, REG1, REG2; \
102 casa [TSB] ASI_PHYS_USE_EC, REG1, REG2; \
105 #define TSB_CAS_TAG(TSB, REG1, REG2) \ argument
106 661: casxa [TSB] ASI_N, REG1, REG2; \
109 casxa [TSB] ASI_PHYS_USE_EC, REG1, REG2; \
119 #define TSB_LOCK_TAG(TSB, REG1, REG2) \ argument
121 sethi %hi(TSB_TAG_LOCK_HIGH), REG2;\
122 andcc REG1, REG2, %g0; \
125 TSB_CAS_TAG_HIGH(TSB, REG1, REG2); \
126 cmp REG1, REG2; \
155 #define KERN_PGTABLE_WALK(VADDR, REG1, REG2, FAIL_LABEL) \ argument
158 sllx VADDR, 64 - (PGDIR_SHIFT + PGDIR_BITS), REG2; \
159 srlx REG2, 64 - PAGE_SHIFT, REG2; \
160 andn REG2, 0x7, REG2; \
161 ldx [REG1 + REG2], REG1; \
163 sllx VADDR, 64 - (PUD_SHIFT + PUD_BITS), REG2; \
164 srlx REG2, 64 - PAGE_SHIFT, REG2; \
165 andn REG2, 0x7, REG2; \
166 ldxa [REG1 + REG2] ASI_PHYS_USE_EC, REG1; \
168 sethi %uhi(_PAGE_PUD_HUGE), REG2; \
170 sllx REG2, 32, REG2; \
171 andcc REG1, REG2, %g0; \
172 sethi %hi(0xf8000000), REG2; \
174 sllx REG2, 1, REG2; \
175 sllx VADDR, 64 - (PMD_SHIFT + PMD_BITS), REG2; \
176 srlx REG2, 64 - PAGE_SHIFT, REG2; \
177 andn REG2, 0x7, REG2; \
178 ldxa [REG1 + REG2] ASI_PHYS_USE_EC, REG1; \
179 sethi %uhi(_PAGE_PMD_HUGE), REG2; \
181 sllx REG2, 32, REG2; \
182 andcc REG1, REG2, %g0; \
184 sethi %hi(0x400000), REG2; \
186 andn REG1, REG2, REG1; \
187 and VADDR, REG2, REG2; \
189 or REG1, REG2, REG1; \
190 698: sllx VADDR, 64 - PMD_SHIFT, REG2; \
191 srlx REG2, 64 - PAGE_SHIFT, REG2; \
192 andn REG2, 0x7, REG2; \
193 ldxa [REG1 + REG2] ASI_PHYS_USE_EC, REG1; \
207 #define USER_PGTABLE_CHECK_PMD_HUGE(VADDR, REG1, REG2, FAIL_LABEL, PTE_LABEL) \ argument
209 sethi %uhi(_PAGE_PMD_HUGE), REG2; \
210 sllx REG2, 32, REG2; \
211 andcc REG1, REG2, %g0; \
213 sethi %hi(4 * 1024 * 1024), REG2; \
215 andn REG1, REG2, REG1; \
216 and VADDR, REG2, REG2; \
218 or REG1, REG2, REG1; \
221 #define USER_PGTABLE_CHECK_PMD_HUGE(VADDR, REG1, REG2, FAIL_LABEL, PTE_LABEL) \ argument
235 #define USER_PGTABLE_WALK_TL1(VADDR, PHYS_PGD, REG1, REG2, FAIL_LABEL) \ argument
236 sllx VADDR, 64 - (PGDIR_SHIFT + PGDIR_BITS), REG2; \
237 srlx REG2, 64 - PAGE_SHIFT, REG2; \
238 andn REG2, 0x7, REG2; \
239 ldxa [PHYS_PGD + REG2] ASI_PHYS_USE_EC, REG1; \
241 sllx VADDR, 64 - (PUD_SHIFT + PUD_BITS), REG2; \
242 srlx REG2, 64 - PAGE_SHIFT, REG2; \
243 andn REG2, 0x7, REG2; \
244 ldxa [REG1 + REG2] ASI_PHYS_USE_EC, REG1; \
246 sllx VADDR, 64 - (PMD_SHIFT + PMD_BITS), REG2; \
247 srlx REG2, 64 - PAGE_SHIFT, REG2; \
248 andn REG2, 0x7, REG2; \
249 ldxa [REG1 + REG2] ASI_PHYS_USE_EC, REG1; \
250 USER_PGTABLE_CHECK_PMD_HUGE(VADDR, REG1, REG2, FAIL_LABEL, 800f) \
251 sllx VADDR, 64 - PMD_SHIFT, REG2; \
252 srlx REG2, 64 - PAGE_SHIFT, REG2; \
253 andn REG2, 0x7, REG2; \
254 add REG1, REG2, REG1; \
265 #define OBP_TRANS_LOOKUP(VADDR, REG1, REG2, REG3, FAIL_LABEL) \ argument
268 97: ldx [REG1 + 0x00], REG2; \
269 brz,pn REG2, FAIL_LABEL; \
272 add REG2, REG3, REG3; \
273 cmp REG2, VADDR; \
278 sub VADDR, REG2, REG2; \
280 add REG3, REG2, REG1; \
301 #define KERN_TSB_LOOKUP_TL1(VADDR, TAG, REG1, REG2, REG3, REG4, OK_LABEL) \ argument
303 sethi %hi(swapper_tsb), REG2; \
305 or REG2, %lo(swapper_tsb), REG2; \
310 or REG1, REG2, REG1; \
311 srlx VADDR, PAGE_SHIFT, REG2; \
312 and REG2, (KERNEL_TSB_NENTRIES - 1), REG2; \
313 sllx REG2, 4, REG2; \
314 add REG1, REG2, REG2; \
315 TSB_LOAD_QUAD(REG2, REG3); \
324 #define KERN_TSB4M_LOOKUP_TL1(TAG, REG1, REG2, REG3, REG4, OK_LABEL) \ argument
326 sethi %hi(swapper_4m_tsb), REG2; \
328 or REG2, %lo(swapper_4m_tsb), REG2; \
333 or REG1, REG2, REG1; \
334 and TAG, (KERNEL_TSB4M_NENTRIES - 1), REG2; \
335 sllx REG2, 4, REG2; \
336 add REG1, REG2, REG2; \
337 TSB_LOAD_QUAD(REG2, REG3); \