28 	if (psw_bits(regs->psw).eaba == PSW_AMODE_24BIT)  in arch_uprobe_pre_xol()
30 	if (!is_compat_task() && psw_bits(regs->psw).eaba == PSW_AMODE_31BIT)  in arch_uprobe_pre_xol()
33 	auprobe->saved_per = psw_bits(regs->psw).r;  in arch_uprobe_pre_xol()
36 	regs->psw.addr = current->utask->xol_vaddr;  in arch_uprobe_pre_xol()
54 	if (!(regs->psw.mask & PSW_MASK_PER))  in check_per_event()
68 		    regs->psw.addr >= current->thread.per_user.start &&  in check_per_event()
69 		    regs->psw.addr <= current->thread.per_user.end)  in check_per_event()
82 	psw_bits(regs->psw).r = auprobe->saved_per;  in arch_uprobe_post_xol()
86 		regs->psw.addr += utask->vaddr - utask->xol_vaddr;  in arch_uprobe_post_xol()
95 		if (regs->psw.addr - utask->xol_vaddr == ilen)  in arch_uprobe_post_xol()
96 			regs->psw.addr = utask->vaddr + ilen;  in arch_uprobe_post_xol()
136 	regs->psw.addr = current->utask->vaddr;  in arch_uprobe_abort_xol()
152 static void adjust_psw_addr(psw_t *psw, unsigned long len)  in adjust_psw_addr()  argument
154 	psw->addr = __rewind_psw(*psw, -len);  in adjust_psw_addr()
210 		psw_bits((regs)->psw).cc = 1;		\
212 		psw_bits((regs)->psw).cc = 2;		\
214 		psw_bits((regs)->psw).cc = 0;		\
240 	if (!(regs->psw.mask & PSW_MASK_PER))  in sim_stor_event()
248 	current->thread.per_event.address = regs->psw.addr;  in sim_stor_event()
267 	uptr = (void *)(regs->psw.addr + (insn->disp * 2));  in handle_insn_ril()
354 	adjust_psw_addr(&regs->psw, ilen);  in handle_insn_ril()
373 	if ((psw_bits(regs->psw).eaba == PSW_AMODE_24BIT) ||  in arch_uprobe_skip_sstep()
374 	    ((psw_bits(regs->psw).eaba == PSW_AMODE_31BIT) &&  in arch_uprobe_skip_sstep()
376 		regs->psw.addr = __rewind_psw(regs->psw, UPROBE_SWBP_INSN_SIZE);  in arch_uprobe_skip_sstep()