Lines Matching refs:PPC403
1887 #define PPC403 PPC_OPCODE_403 macro
1888 #define PPC405 PPC403
3060 { "rfci", XL(19,51), 0xffffffff, PPC403 | BOOKE, { 0 } },
3398 { "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } },
3479 { "dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440, { RA, RS, RB } },
3480 { "dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440, { RA, RS, RB } },
3524 { "wrtee", X(31,131), XRARB_MASK, PPC403 | BOOKE, { RS } },
3573 { "wrteei", X(31,163), XE_MASK, PPC403 | BOOKE, { E } },
3719 { "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403, { RT } },
3720 { "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403, { RT } },
3721 { "mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, { RT } },
3722 { "mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, { RT } },
3723 { "mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, { RT } },
3724 { "mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, { RT } },
3725 { "mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, { RT } },
3726 { "mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, { RT } },
3727 { "mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, { RT } },
3728 { "mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, { RT } },
3729 { "mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, { RT } },
3730 { "mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, { RT } },
3731 { "mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, { RT } },
3732 { "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, { RT } },
3733 { "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, { RT } },
3734 { "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, { RT } },
3735 { "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, { RT } },
3736 { "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, { RT } },
3737 { "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, { RT } },
3738 { "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, { RT } },
3739 { "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, { RT } },
3740 { "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, { RT } },
3741 { "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, { RT } },
3742 { "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, { RT } },
3743 { "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, { RT } },
3744 { "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, { RT } },
3745 { "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, { RT } },
3746 { "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, { RT } },
3747 { "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, { RT } },
3748 { "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, { RT } },
3749 { "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, { RT } },
3750 { "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT } },
3751 { "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } },
3752 { "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } },
3753 { "mfdcr", X(31,323), X_MASK, PPC403 | BOOKE, { RT, SPR } },
3779 { "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } },
3783 { "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } },
3785 { "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } },
3825 { "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } },
3832 { "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } },
3834 { "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } },
3840 { "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } },
3842 { "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } },
3848 { "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } },
3850 { "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } },
3917 { "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } },
3921 { "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT } },
3923 { "mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, { RT } },
3930 { "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } },
3931 { "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } },
3932 { "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT } },
3933 { "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT } },
3934 { "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT } },
3935 { "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT } },
3936 { "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } },
3937 { "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } },
3939 { "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } },
3940 { "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } },
3942 { "mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, { RT } },
3944 { "mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, { RT } },
3946 { "mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, { RT } },
3948 { "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } },
3963 { "dccci", X(31,454), XRT_MASK, PPC403|PPC440, { RA, RB } },
4034 { "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RS } },
4035 { "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RS } },
4036 { "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RS } },
4037 { "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RS } },
4038 { "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RS } },
4039 { "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RS } },
4040 { "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RS } },
4041 { "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RS } },
4042 { "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RS } },
4043 { "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RS } },
4044 { "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RS } },
4045 { "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RS } },
4046 { "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RS } },
4047 { "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RS } },
4048 { "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RS } },
4049 { "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RS } },
4050 { "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RS } },
4051 { "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RS } },
4052 { "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RS } },
4053 { "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RS } },
4054 { "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RS } },
4055 { "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RS } },
4056 { "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RS } },
4057 { "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RS } },
4058 { "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RS } },
4059 { "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RS } },
4060 { "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RS } },
4061 { "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RS } },
4062 { "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RS } },
4063 { "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RS } },
4064 { "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RS } },
4065 { "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RS } },
4066 { "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RS } },
4067 { "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RS } },
4068 { "mtdcr", X(31,451), X_MASK, PPC403 | BOOKE, { SPR, RS } },
4102 { "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RS } },
4107 { "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RS } },
4109 { "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RS } },
4143 { "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RS } },
4150 { "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RS } },
4152 { "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RS } },
4158 { "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RS } },
4160 { "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RS } },
4166 { "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RS } },
4168 { "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RS } },
4206 { "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RS } },
4209 { "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RS } },
4211 { "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RS } },
4219 { "mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, { RS } },
4220 { "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RS } },
4221 { "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RS } },
4222 { "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RS } },
4223 { "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RS } },
4224 { "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RS } },
4225 { "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RS } },
4226 { "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RS } },
4228 { "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RS } },
4229 { "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RS } },
4231 { "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RS } },
4233 { "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RS } },
4235 { "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RS } },
4237 { "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RS } },
4247 { "dcread", X(31,486), X_MASK, PPC403|PPC440, { RT, RA, RB }},
4447 { "tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE, { RTO, RA, RB } },
4448 { "tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE, { RTO, RA, RB } },
4473 { "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } },
4474 { "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } },
4475 { "tlbre", X(31,946), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } },
4487 { "iccci", X(31,966), XRT_MASK, PPC403|PPC440, { RA, RB } },
4489 { "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } },
4490 { "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } },
4491 { "tlbwe", X(31,978), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } },
4503 { "icread", X(31,998), XRT_MASK, PPC403|PPC440, { RA, RB } },