649 	unsigned int		sdr_base;  member
679 		val = mfdcri(SDR0, port->sdr_base + sdr_offset);  in ppc4xx_pciex_wait_on_sdr()
863 	mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);  in ppc440spe_pciex_init_port_hw()
864 	mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x20222222);  in ppc440spe_pciex_init_port_hw()
866 		mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x11000000);  in ppc440spe_pciex_init_port_hw()
867 	mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL0SET1, 0x35000000);  in ppc440spe_pciex_init_port_hw()
868 	mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL1SET1, 0x35000000);  in ppc440spe_pciex_init_port_hw()
869 	mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL2SET1, 0x35000000);  in ppc440spe_pciex_init_port_hw()
870 	mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL3SET1, 0x35000000);  in ppc440spe_pciex_init_port_hw()
872 		mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL4SET1,  in ppc440spe_pciex_init_port_hw()
874 		mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL5SET1,  in ppc440spe_pciex_init_port_hw()
876 		mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL6SET1,  in ppc440spe_pciex_init_port_hw()
878 		mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL7SET1,  in ppc440spe_pciex_init_port_hw()
881 	dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET,  in ppc440spe_pciex_init_port_hw()
971 	mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);  in ppc460ex_pciex_init_port_hw()
972 	mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, utlset1);  in ppc460ex_pciex_init_port_hw()
973 	mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01210000);  in ppc460ex_pciex_init_port_hw()
1002 	mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,  in ppc460ex_pciex_init_port_hw()
1003 	       mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |  in ppc460ex_pciex_init_port_hw()
1019 	mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,  in ppc460ex_pciex_init_port_hw()
1020 	       (mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) &  in ppc460ex_pciex_init_port_hw()
1086 	mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);  in apm821xx_pciex_init_port_hw()
1087 	mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000);  in apm821xx_pciex_init_port_hw()
1088 	mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000);  in apm821xx_pciex_init_port_hw()
1098 	mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,  in apm821xx_pciex_init_port_hw()
1099 		mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |  in apm821xx_pciex_init_port_hw()
1103 	val = PESDR0_460EX_RSTSTA - port->sdr_base;  in apm821xx_pciex_init_port_hw()
1108 		mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,  in apm821xx_pciex_init_port_hw()
1109 			(mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) &  in apm821xx_pciex_init_port_hw()
1216 		dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2,  in ppc460sx_pciex_init_port_hw()
1219 		dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2,  in ppc460sx_pciex_init_port_hw()
1222 	dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET,  in ppc460sx_pciex_init_port_hw()
1287 	mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01010000);  in ppc405ex_pcie_phy_reset()
1292 		mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01111000);  in ppc405ex_pcie_phy_reset()
1294 		mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01101000);  in ppc405ex_pcie_phy_reset()
1298 	while (!(mfdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSTA) & 0x00001000))  in ppc405ex_pcie_phy_reset()
1302 	mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x00101000);  in ppc405ex_pcie_phy_reset()
1314 	mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET,  in ppc405ex_pciex_init_port_hw()
1317 	mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000);  in ppc405ex_pciex_init_port_hw()
1318 	mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000);  in ppc405ex_pciex_init_port_hw()
1319 	mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET1, 0x720F0000);  in ppc405ex_pciex_init_port_hw()
1320 	mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET2, 0x70600003);  in ppc405ex_pciex_init_port_hw()
1329 	val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);  in ppc405ex_pciex_init_port_hw()
1532 	if (port->sdr_base) {  in ppc4xx_pciex_port_init()
1550 		dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20);  in ppc4xx_pciex_port_init()
2132 		port->sdr_base = *pval;  in ppc4xx_probe_pciex_bridge()