Lines Matching refs:port
663 int (*port_init_hw)(struct ppc4xx_pciex_port *port);
664 int (*setup_utl)(struct ppc4xx_pciex_port *port);
665 void (*check_link)(struct ppc4xx_pciex_port *port);
670 static int __init ppc4xx_pciex_wait_on_sdr(struct ppc4xx_pciex_port *port, in ppc4xx_pciex_wait_on_sdr() argument
679 val = mfdcri(SDR0, port->sdr_base + sdr_offset); in ppc4xx_pciex_wait_on_sdr()
682 port->index, sdr_offset, timeout_ms, val); in ppc4xx_pciex_wait_on_sdr()
690 static int __init ppc4xx_pciex_port_reset_sdr(struct ppc4xx_pciex_port *port) in ppc4xx_pciex_port_reset_sdr() argument
693 if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS, 1 << 20, 0, 10)) { in ppc4xx_pciex_port_reset_sdr()
695 port->index); in ppc4xx_pciex_port_reset_sdr()
702 static void __init ppc4xx_pciex_check_link_sdr(struct ppc4xx_pciex_port *port) in ppc4xx_pciex_check_link_sdr() argument
704 printk(KERN_INFO "PCIE%d: Checking link...\n", port->index); in ppc4xx_pciex_check_link_sdr()
713 if (!port->has_ibpre || in ppc4xx_pciex_check_link_sdr()
714 !ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP, in ppc4xx_pciex_check_link_sdr()
718 port->index); in ppc4xx_pciex_check_link_sdr()
719 if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP, in ppc4xx_pciex_check_link_sdr()
722 "PCIE%d: Link up failed\n", port->index); in ppc4xx_pciex_check_link_sdr()
725 "PCIE%d: link is up !\n", port->index); in ppc4xx_pciex_check_link_sdr()
726 port->link = 1; in ppc4xx_pciex_check_link_sdr()
729 printk(KERN_INFO "PCIE%d: No device detected.\n", port->index); in ppc4xx_pciex_check_link_sdr()
849 static int __init ppc440spe_pciex_init_port_hw(struct ppc4xx_pciex_port *port) in ppc440spe_pciex_init_port_hw() argument
853 if (port->endpoint) in ppc440spe_pciex_init_port_hw()
858 if (port->index == 0) in ppc440spe_pciex_init_port_hw()
863 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val); in ppc440spe_pciex_init_port_hw()
864 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x20222222); in ppc440spe_pciex_init_port_hw()
866 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x11000000); in ppc440spe_pciex_init_port_hw()
867 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL0SET1, 0x35000000); in ppc440spe_pciex_init_port_hw()
868 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL1SET1, 0x35000000); in ppc440spe_pciex_init_port_hw()
869 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL2SET1, 0x35000000); in ppc440spe_pciex_init_port_hw()
870 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL3SET1, 0x35000000); in ppc440spe_pciex_init_port_hw()
871 if (port->index == 0) { in ppc440spe_pciex_init_port_hw()
872 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL4SET1, in ppc440spe_pciex_init_port_hw()
874 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL5SET1, in ppc440spe_pciex_init_port_hw()
876 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL6SET1, in ppc440spe_pciex_init_port_hw()
878 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL7SET1, in ppc440spe_pciex_init_port_hw()
881 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, in ppc440spe_pciex_init_port_hw()
884 return ppc4xx_pciex_port_reset_sdr(port); in ppc440spe_pciex_init_port_hw()
887 static int __init ppc440speA_pciex_init_port_hw(struct ppc4xx_pciex_port *port) in ppc440speA_pciex_init_port_hw() argument
889 return ppc440spe_pciex_init_port_hw(port); in ppc440speA_pciex_init_port_hw()
892 static int __init ppc440speB_pciex_init_port_hw(struct ppc4xx_pciex_port *port) in ppc440speB_pciex_init_port_hw() argument
894 int rc = ppc440spe_pciex_init_port_hw(port); in ppc440speB_pciex_init_port_hw()
896 port->has_ibpre = 1; in ppc440speB_pciex_init_port_hw()
901 static int ppc440speA_pciex_init_utl(struct ppc4xx_pciex_port *port) in ppc440speA_pciex_init_utl() argument
904 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x68782800); in ppc440speA_pciex_init_utl()
909 out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000); in ppc440speA_pciex_init_utl()
910 out_be32(port->utl_base + PEUTL_INTR, 0x02000000); in ppc440speA_pciex_init_utl()
911 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x10000000); in ppc440speA_pciex_init_utl()
912 out_be32(port->utl_base + PEUTL_PBBSZ, 0x53000000); in ppc440speA_pciex_init_utl()
913 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x08000000); in ppc440speA_pciex_init_utl()
914 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x10000000); in ppc440speA_pciex_init_utl()
915 out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000); in ppc440speA_pciex_init_utl()
916 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066); in ppc440speA_pciex_init_utl()
921 static int ppc440speB_pciex_init_utl(struct ppc4xx_pciex_port *port) in ppc440speB_pciex_init_utl() argument
924 out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000); in ppc440speB_pciex_init_utl()
953 static int __init ppc460ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port) in ppc460ex_pciex_init_port_hw() argument
958 if (port->endpoint) in ppc460ex_pciex_init_port_hw()
963 if (port->index == 0) { in ppc460ex_pciex_init_port_hw()
971 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val); in ppc460ex_pciex_init_port_hw()
972 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, utlset1); in ppc460ex_pciex_init_port_hw()
973 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01210000); in ppc460ex_pciex_init_port_hw()
975 switch (port->index) { in ppc460ex_pciex_init_port_hw()
1002 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, in ppc460ex_pciex_init_port_hw()
1003 mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) | in ppc460ex_pciex_init_port_hw()
1008 switch (port->index) { in ppc460ex_pciex_init_port_hw()
1019 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, in ppc460ex_pciex_init_port_hw()
1020 (mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) & in ppc460ex_pciex_init_port_hw()
1024 port->has_ibpre = 1; in ppc460ex_pciex_init_port_hw()
1026 return ppc4xx_pciex_port_reset_sdr(port); in ppc460ex_pciex_init_port_hw()
1029 static int ppc460ex_pciex_init_utl(struct ppc4xx_pciex_port *port) in ppc460ex_pciex_init_utl() argument
1031 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0); in ppc460ex_pciex_init_utl()
1036 out_be32(port->utl_base + PEUTL_PBCTL, 0x0800000c); in ppc460ex_pciex_init_utl()
1037 out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000); in ppc460ex_pciex_init_utl()
1038 out_be32(port->utl_base + PEUTL_INTR, 0x02000000); in ppc460ex_pciex_init_utl()
1039 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000); in ppc460ex_pciex_init_utl()
1040 out_be32(port->utl_base + PEUTL_PBBSZ, 0x00000000); in ppc460ex_pciex_init_utl()
1041 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000); in ppc460ex_pciex_init_utl()
1042 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000); in ppc460ex_pciex_init_utl()
1043 out_be32(port->utl_base + PEUTL_RCIRQEN,0x00f00000); in ppc460ex_pciex_init_utl()
1044 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066); in ppc460ex_pciex_init_utl()
1064 static int __init apm821xx_pciex_init_port_hw(struct ppc4xx_pciex_port *port) in apm821xx_pciex_init_port_hw() argument
1079 if (port->endpoint) in apm821xx_pciex_init_port_hw()
1086 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val); in apm821xx_pciex_init_port_hw()
1087 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000); in apm821xx_pciex_init_port_hw()
1088 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000); in apm821xx_pciex_init_port_hw()
1098 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, in apm821xx_pciex_init_port_hw()
1099 mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) | in apm821xx_pciex_init_port_hw()
1103 val = PESDR0_460EX_RSTSTA - port->sdr_base; in apm821xx_pciex_init_port_hw()
1104 if (ppc4xx_pciex_wait_on_sdr(port, val, 0x1, 1, 100)) { in apm821xx_pciex_init_port_hw()
1108 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, in apm821xx_pciex_init_port_hw()
1109 (mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) & in apm821xx_pciex_init_port_hw()
1113 port->has_ibpre = 1; in apm821xx_pciex_init_port_hw()
1212 static int __init ppc460sx_pciex_init_port_hw(struct ppc4xx_pciex_port *port) in ppc460sx_pciex_init_port_hw() argument
1215 if (port->endpoint) in ppc460sx_pciex_init_port_hw()
1216 dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2, in ppc460sx_pciex_init_port_hw()
1219 dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2, in ppc460sx_pciex_init_port_hw()
1222 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, in ppc460sx_pciex_init_port_hw()
1226 port->has_ibpre = 1; in ppc460sx_pciex_init_port_hw()
1228 return ppc4xx_pciex_port_reset_sdr(port); in ppc460sx_pciex_init_port_hw()
1231 static int ppc460sx_pciex_init_utl(struct ppc4xx_pciex_port *port) in ppc460sx_pciex_init_utl() argument
1234 out_be32 (port->utl_base + PEUTL_PBBSZ, 0x00000000); in ppc460sx_pciex_init_utl()
1236 out_be32(port->utl_base + PEUTL_PCTL, 0x80800000); in ppc460sx_pciex_init_utl()
1240 static void __init ppc460sx_pciex_check_link(struct ppc4xx_pciex_port *port) in ppc460sx_pciex_check_link() argument
1245 port->link = 0; in ppc460sx_pciex_check_link()
1247 mbase = ioremap(port->cfg_space.start + 0x10000000, 0x1000); in ppc460sx_pciex_check_link()
1250 port->node->full_name); in ppc460sx_pciex_check_link()
1260 port->link = 1; in ppc460sx_pciex_check_link()
1284 static void ppc405ex_pcie_phy_reset(struct ppc4xx_pciex_port *port) in ppc405ex_pcie_phy_reset() argument
1287 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01010000); in ppc405ex_pcie_phy_reset()
1291 if (port->endpoint) in ppc405ex_pcie_phy_reset()
1292 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01111000); in ppc405ex_pcie_phy_reset()
1294 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01101000); in ppc405ex_pcie_phy_reset()
1298 while (!(mfdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSTA) & 0x00001000)) in ppc405ex_pcie_phy_reset()
1302 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x00101000); in ppc405ex_pcie_phy_reset()
1305 static int __init ppc405ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port) in ppc405ex_pciex_init_port_hw() argument
1309 if (port->endpoint) in ppc405ex_pciex_init_port_hw()
1314 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, in ppc405ex_pciex_init_port_hw()
1317 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000); in ppc405ex_pciex_init_port_hw()
1318 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000); in ppc405ex_pciex_init_port_hw()
1319 mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET1, 0x720F0000); in ppc405ex_pciex_init_port_hw()
1320 mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET2, 0x70600003); in ppc405ex_pciex_init_port_hw()
1329 val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP); in ppc405ex_pciex_init_port_hw()
1331 ppc405ex_pcie_phy_reset(port); in ppc405ex_pciex_init_port_hw()
1333 dcr_write(port->dcrs, DCRO_PEGPL_CFG, 0x10000000); /* guarded on */ in ppc405ex_pciex_init_port_hw()
1335 port->has_ibpre = 1; in ppc405ex_pciex_init_port_hw()
1337 return ppc4xx_pciex_port_reset_sdr(port); in ppc405ex_pciex_init_port_hw()
1340 static int ppc405ex_pciex_init_utl(struct ppc4xx_pciex_port *port) in ppc405ex_pciex_init_utl() argument
1342 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0); in ppc405ex_pciex_init_utl()
1347 out_be32(port->utl_base + PEUTL_OUTTR, 0x02000000); in ppc405ex_pciex_init_utl()
1348 out_be32(port->utl_base + PEUTL_INTR, 0x02000000); in ppc405ex_pciex_init_utl()
1349 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000); in ppc405ex_pciex_init_utl()
1350 out_be32(port->utl_base + PEUTL_PBBSZ, 0x21000000); in ppc405ex_pciex_init_utl()
1351 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000); in ppc405ex_pciex_init_utl()
1352 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000); in ppc405ex_pciex_init_utl()
1353 out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000); in ppc405ex_pciex_init_utl()
1354 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066); in ppc405ex_pciex_init_utl()
1356 out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000); in ppc405ex_pciex_init_utl()
1378 static void __init ppc_476fpe_pciex_check_link(struct ppc4xx_pciex_port *port) in ppc_476fpe_pciex_check_link() argument
1382 void __iomem *mbase = ioremap(port->cfg_space.start + 0x10000000, in ppc_476fpe_pciex_check_link()
1385 printk(KERN_INFO "PCIE%d: Checking link...\n", port->index); in ppc_476fpe_pciex_check_link()
1389 port->index); in ppc_476fpe_pciex_check_link()
1402 printk(KERN_INFO "PCIE%d: link is up !\n", port->index); in ppc_476fpe_pciex_check_link()
1403 port->link = 1; in ppc_476fpe_pciex_check_link()
1405 printk(KERN_WARNING "PCIE%d: Link up failed\n", port->index); in ppc_476fpe_pciex_check_link()
1471 static void __init ppc4xx_pciex_port_init_mapping(struct ppc4xx_pciex_port *port) in ppc4xx_pciex_port_init_mapping() argument
1474 dcr_write(port->dcrs, DCRO_PEGPL_CFGBAH, in ppc4xx_pciex_port_init_mapping()
1475 RES_TO_U32_HIGH(port->cfg_space.start)); in ppc4xx_pciex_port_init_mapping()
1476 dcr_write(port->dcrs, DCRO_PEGPL_CFGBAL, in ppc4xx_pciex_port_init_mapping()
1477 RES_TO_U32_LOW(port->cfg_space.start)); in ppc4xx_pciex_port_init_mapping()
1480 dcr_write(port->dcrs, DCRO_PEGPL_CFGMSK, 0xe0000001); in ppc4xx_pciex_port_init_mapping()
1483 dcr_write(port->dcrs, DCRO_PEGPL_REGBAH, in ppc4xx_pciex_port_init_mapping()
1484 RES_TO_U32_HIGH(port->utl_regs.start)); in ppc4xx_pciex_port_init_mapping()
1485 dcr_write(port->dcrs, DCRO_PEGPL_REGBAL, in ppc4xx_pciex_port_init_mapping()
1486 RES_TO_U32_LOW(port->utl_regs.start)); in ppc4xx_pciex_port_init_mapping()
1489 dcr_write(port->dcrs, DCRO_PEGPL_REGMSK, 0x00007001); in ppc4xx_pciex_port_init_mapping()
1492 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, 0); in ppc4xx_pciex_port_init_mapping()
1493 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, 0); in ppc4xx_pciex_port_init_mapping()
1494 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, 0); in ppc4xx_pciex_port_init_mapping()
1495 dcr_write(port->dcrs, DCRO_PEGPL_MSGMSK, 0); in ppc4xx_pciex_port_init_mapping()
1498 static int __init ppc4xx_pciex_port_init(struct ppc4xx_pciex_port *port) in ppc4xx_pciex_port_init() argument
1504 rc = ppc4xx_pciex_hwops->port_init_hw(port); in ppc4xx_pciex_port_init()
1512 ppc4xx_pciex_port_init_mapping(port); in ppc4xx_pciex_port_init()
1515 ppc4xx_pciex_hwops->check_link(port); in ppc4xx_pciex_port_init()
1520 port->utl_base = ioremap(port->utl_regs.start, 0x100); in ppc4xx_pciex_port_init()
1521 BUG_ON(port->utl_base == NULL); in ppc4xx_pciex_port_init()
1527 ppc4xx_pciex_hwops->setup_utl(port); in ppc4xx_pciex_port_init()
1532 if (port->sdr_base) { in ppc4xx_pciex_port_init()
1533 if (of_device_is_compatible(port->node, in ppc4xx_pciex_port_init()
1535 if (port->link && ppc4xx_pciex_wait_on_sdr(port, in ppc4xx_pciex_port_init()
1539 port->index); in ppc4xx_pciex_port_init()
1540 port->link = 0; in ppc4xx_pciex_port_init()
1542 } else if (port->link && in ppc4xx_pciex_port_init()
1543 ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS, in ppc4xx_pciex_port_init()
1546 port->index); in ppc4xx_pciex_port_init()
1547 port->link = 0; in ppc4xx_pciex_port_init()
1550 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20); in ppc4xx_pciex_port_init()
1558 static int ppc4xx_pciex_validate_bdf(struct ppc4xx_pciex_port *port, in ppc4xx_pciex_validate_bdf() argument
1565 if (port->endpoint && bus->number != port->hose->first_busno) in ppc4xx_pciex_validate_bdf()
1569 if (bus->number > port->hose->last_busno) { in ppc4xx_pciex_validate_bdf()
1579 if (bus->number == port->hose->first_busno && devfn != 0) in ppc4xx_pciex_validate_bdf()
1583 if (bus->number == (port->hose->first_busno + 1) && in ppc4xx_pciex_validate_bdf()
1588 if ((bus->number != port->hose->first_busno) && !port->link) in ppc4xx_pciex_validate_bdf()
1594 static void __iomem *ppc4xx_pciex_get_config_base(struct ppc4xx_pciex_port *port, in ppc4xx_pciex_get_config_base() argument
1603 if (bus->number == port->hose->first_busno) in ppc4xx_pciex_get_config_base()
1604 return (void __iomem *)port->hose->cfg_addr; in ppc4xx_pciex_get_config_base()
1606 relbus = bus->number - (port->hose->first_busno + 1); in ppc4xx_pciex_get_config_base()
1607 return (void __iomem *)port->hose->cfg_data + in ppc4xx_pciex_get_config_base()
1615 struct ppc4xx_pciex_port *port = in ppc4xx_pciex_read_config() local
1620 BUG_ON(hose != port->hose); in ppc4xx_pciex_read_config()
1622 if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0) in ppc4xx_pciex_read_config()
1625 addr = ppc4xx_pciex_get_config_base(port, bus, devfn); in ppc4xx_pciex_read_config()
1632 gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG); in ppc4xx_pciex_read_config()
1633 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA); in ppc4xx_pciex_read_config()
1636 out_be32(port->utl_base + PEUTL_RCSTA, 0x00040000); in ppc4xx_pciex_read_config()
1656 if (in_be32(port->utl_base + PEUTL_RCSTA) & 0x00040000) { in ppc4xx_pciex_read_config()
1663 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg); in ppc4xx_pciex_read_config()
1672 struct ppc4xx_pciex_port *port = in ppc4xx_pciex_write_config() local
1677 if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0) in ppc4xx_pciex_write_config()
1680 addr = ppc4xx_pciex_get_config_base(port, bus, devfn); in ppc4xx_pciex_write_config()
1687 gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG); in ppc4xx_pciex_write_config()
1688 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA); in ppc4xx_pciex_write_config()
1707 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg); in ppc4xx_pciex_write_config()
1718 static int __init ppc4xx_setup_one_pciex_POM(struct ppc4xx_pciex_port *port, in ppc4xx_setup_one_pciex_POM() argument
1750 dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAH, lah); in ppc4xx_setup_one_pciex_POM()
1751 dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAL, lal); in ppc4xx_setup_one_pciex_POM()
1752 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKH, 0x7fffffff); in ppc4xx_setup_one_pciex_POM()
1754 if (of_device_is_compatible(port->node, "ibm,plb-pciex-460sx")) in ppc4xx_setup_one_pciex_POM()
1755 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, in ppc4xx_setup_one_pciex_POM()
1759 port->node, "ibm,plb-pciex-476fpe") || in ppc4xx_setup_one_pciex_POM()
1761 port->node, "ibm,plb-pciex-476gtr")) in ppc4xx_setup_one_pciex_POM()
1762 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, in ppc4xx_setup_one_pciex_POM()
1766 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, in ppc4xx_setup_one_pciex_POM()
1773 dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAH, lah); in ppc4xx_setup_one_pciex_POM()
1774 dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAL, lal); in ppc4xx_setup_one_pciex_POM()
1775 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKH, 0x7fffffff); in ppc4xx_setup_one_pciex_POM()
1776 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, in ppc4xx_setup_one_pciex_POM()
1782 dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAH, lah); in ppc4xx_setup_one_pciex_POM()
1783 dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAL, lal); in ppc4xx_setup_one_pciex_POM()
1784 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKH, 0x7fffffff); in ppc4xx_setup_one_pciex_POM()
1786 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, in ppc4xx_setup_one_pciex_POM()
1795 static void __init ppc4xx_configure_pciex_POMs(struct ppc4xx_pciex_port *port, in ppc4xx_configure_pciex_POMs() argument
1811 port->node->full_name); in ppc4xx_configure_pciex_POMs()
1816 if (ppc4xx_setup_one_pciex_POM(port, hose, mbase, in ppc4xx_configure_pciex_POMs()
1834 if (ppc4xx_setup_one_pciex_POM(port, hose, mbase, in ppc4xx_configure_pciex_POMs()
1844 ppc4xx_setup_one_pciex_POM(port, hose, mbase, in ppc4xx_configure_pciex_POMs()
1849 static void __init ppc4xx_configure_pciex_PIMs(struct ppc4xx_pciex_port *port, in ppc4xx_configure_pciex_PIMs() argument
1857 if (port->endpoint) { in ppc4xx_configure_pciex_PIMs()
1890 if (of_device_is_compatible(port->node, "ibm,plb-pciex-460sx") || in ppc4xx_configure_pciex_PIMs()
1892 port->node, "ibm,plb-pciex-476fpe") || in ppc4xx_configure_pciex_PIMs()
1894 port->node, "ibm,plb-pciex-476gtr")) in ppc4xx_configure_pciex_PIMs()
1923 static void __init ppc4xx_pciex_port_setup_hose(struct ppc4xx_pciex_port *port) in ppc4xx_pciex_port_setup_hose() argument
1934 if (of_get_property(port->node, "primary", NULL)) in ppc4xx_pciex_port_setup_hose()
1938 bus_range = of_get_property(port->node, "bus-range", NULL); in ppc4xx_pciex_port_setup_hose()
1941 hose = pcibios_alloc_controller(port->node); in ppc4xx_pciex_port_setup_hose()
1948 hose->indirect_type = port->index; in ppc4xx_pciex_port_setup_hose()
1965 if (!port->endpoint) { in ppc4xx_pciex_port_setup_hose()
1969 cfg_data = ioremap(port->cfg_space.start + in ppc4xx_pciex_port_setup_hose()
1974 port->node->full_name); in ppc4xx_pciex_port_setup_hose()
1983 mbase = ioremap(port->cfg_space.start + 0x10000000, 0x1000); in ppc4xx_pciex_port_setup_hose()
1986 port->node->full_name); in ppc4xx_pciex_port_setup_hose()
1991 pr_debug("PCIE %s, bus %d..%d\n", port->node->full_name, in ppc4xx_pciex_port_setup_hose()
1998 port->hose = hose; in ppc4xx_pciex_port_setup_hose()
2001 if (!port->endpoint) { in ppc4xx_pciex_port_setup_hose()
2016 pci_process_bridge_OF_ranges(hose, port->node, primary); in ppc4xx_pciex_port_setup_hose()
2023 ppc4xx_configure_pciex_POMs(port, hose, mbase); in ppc4xx_pciex_port_setup_hose()
2026 ppc4xx_configure_pciex_PIMs(port, hose, mbase, &dma_window); in ppc4xx_pciex_port_setup_hose()
2036 pval = of_get_property(port->node, "vendor-id", NULL); in ppc4xx_pciex_port_setup_hose()
2040 if (!port->endpoint) in ppc4xx_pciex_port_setup_hose()
2041 val = 0xaaa0 + port->index; in ppc4xx_pciex_port_setup_hose()
2043 val = 0xeee0 + port->index; in ppc4xx_pciex_port_setup_hose()
2047 pval = of_get_property(port->node, "device-id", NULL); in ppc4xx_pciex_port_setup_hose()
2051 if (!port->endpoint) in ppc4xx_pciex_port_setup_hose()
2052 val = 0xbed0 + port->index; in ppc4xx_pciex_port_setup_hose()
2054 val = 0xfed0 + port->index; in ppc4xx_pciex_port_setup_hose()
2059 if (of_device_is_compatible(port->node, "ibm,plb-pciex-460sx")) in ppc4xx_pciex_port_setup_hose()
2062 if (!port->endpoint) { in ppc4xx_pciex_port_setup_hose()
2067 port->index); in ppc4xx_pciex_port_setup_hose()
2073 port->index); in ppc4xx_pciex_port_setup_hose()
2088 struct ppc4xx_pciex_port *port; in ppc4xx_probe_pciex_bridge() local
2113 port = &ppc4xx_pciex_ports[portno]; in ppc4xx_probe_pciex_bridge()
2114 port->index = portno; in ppc4xx_probe_pciex_bridge()
2120 printk(KERN_INFO "PCIE%d: Port disabled via device-tree\n", port->index); in ppc4xx_probe_pciex_bridge()
2124 port->node = of_node_get(np); in ppc4xx_probe_pciex_bridge()
2132 port->sdr_base = *pval; in ppc4xx_probe_pciex_bridge()
2139 val = of_get_property(port->node, "device_type", NULL); in ppc4xx_probe_pciex_bridge()
2141 port->endpoint = 1; in ppc4xx_probe_pciex_bridge()
2143 port->endpoint = 0; in ppc4xx_probe_pciex_bridge()
2151 if (of_address_to_resource(np, 0, &port->cfg_space)) { in ppc4xx_probe_pciex_bridge()
2157 if (of_address_to_resource(np, 1, &port->utl_regs)) { in ppc4xx_probe_pciex_bridge()
2170 port->dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0)); in ppc4xx_probe_pciex_bridge()
2173 if (ppc4xx_pciex_port_init(port)) { in ppc4xx_probe_pciex_bridge()
2174 printk(KERN_WARNING "PCIE%d: Port init failed\n", port->index); in ppc4xx_probe_pciex_bridge()
2179 ppc4xx_pciex_port_setup_hose(port); in ppc4xx_probe_pciex_bridge()