465 static void iommu_table_setparms(struct pci_controller *phb,  in iommu_table_setparms()  argument
473 	node = phb->dn;  in iommu_table_setparms()
488 	tbl->it_busno = phb->bus->number;  in iommu_table_setparms()
492 	tbl->it_offset = phb->dma_window_base_cur >> tbl->it_page_shift;  in iommu_table_setparms()
495 	if (phb->dma_window_base_cur + phb->dma_window_size > 0x80000000ul) {  in iommu_table_setparms()
500 	phb->dma_window_base_cur += phb->dma_window_size;  in iommu_table_setparms()
503 	tbl->it_size = phb->dma_window_size >> tbl->it_page_shift;  in iommu_table_setparms()
531 static void iommu_table_setparms_lpar(struct pci_controller *phb,  in iommu_table_setparms_lpar()  argument
540 	tbl->it_busno = phb->bus->number;  in iommu_table_setparms_lpar()
594 		pci->phb->dma_window_size = 0x80000000ul; /* To be divided */  in pci_dma_bus_setup_pSeries()
596 		while (pci->phb->dma_window_size * children > 0x80000000ul)  in pci_dma_bus_setup_pSeries()
597 			pci->phb->dma_window_size >>= 1;  in pci_dma_bus_setup_pSeries()
599 			 pci->phb->dma_window_size);  in pci_dma_bus_setup_pSeries()
600 		pci->phb->dma_window_base_cur = 0;  in pci_dma_bus_setup_pSeries()
610 	pci->phb->dma_window_size = 0x8000000ul;  in pci_dma_bus_setup_pSeries()
611 	pci->phb->dma_window_base_cur = 0x8000000ul;  in pci_dma_bus_setup_pSeries()
614 			   pci->phb->node);  in pci_dma_bus_setup_pSeries()
616 	iommu_table_setparms(pci->phb, dn, tbl);  in pci_dma_bus_setup_pSeries()
617 	pci->iommu_table = iommu_init_table(tbl, pci->phb->node);  in pci_dma_bus_setup_pSeries()
621 	pci->phb->dma_window_size = 0x80000000ul;  in pci_dma_bus_setup_pSeries()
622 	while (pci->phb->dma_window_size * children > 0x70000000ul)  in pci_dma_bus_setup_pSeries()
623 		pci->phb->dma_window_size >>= 1;  in pci_dma_bus_setup_pSeries()
625 	pr_debug("ISA/IDE, window size is 0x%llx\n", pci->phb->dma_window_size);  in pci_dma_bus_setup_pSeries()
660 				   ppci->phb->node);  in pci_dma_bus_setup_pSeriesLP()
661 		iommu_table_setparms_lpar(ppci->phb, pdn, tbl, dma_window);  in pci_dma_bus_setup_pSeriesLP()
662 		ppci->iommu_table = iommu_init_table(tbl, ppci->phb->node);  in pci_dma_bus_setup_pSeriesLP()
683 		struct pci_controller *phb = PCI_DN(dn)->phb;  in pci_dma_dev_setup_pSeries()  local
687 				   phb->node);  in pci_dma_dev_setup_pSeries()
688 		iommu_table_setparms(phb, dn, tbl);  in pci_dma_dev_setup_pSeries()
689 		PCI_DN(dn)->iommu_table = iommu_init_table(tbl, phb->node);  in pci_dma_dev_setup_pSeries()
690 		iommu_register_group(tbl, pci_domain_nr(phb->bus), 0);  in pci_dma_dev_setup_pSeries()
843 	buid = edev->phb->buid;  in query_ddw()
872 	buid = edev->phb->buid;  in create_ddw()
1109 				   pci->phb->node);  in pci_dma_dev_setup_pSeriesLP()
1110 		iommu_table_setparms_lpar(pci->phb, pdn, tbl, dma_window);  in pci_dma_dev_setup_pSeriesLP()
1111 		pci->iommu_table = iommu_init_table(tbl, pci->phb->node);  in pci_dma_dev_setup_pSeriesLP()
1112 		iommu_register_group(tbl, pci_domain_nr(pci->phb->bus), 0);  in pci_dma_dev_setup_pSeriesLP()