Lines Matching refs:phb
44 static int pnv_pci_p5ioc2_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, in pnv_pci_p5ioc2_msi_setup() argument
50 msg->data = hwirq - phb->msi_base; in pnv_pci_p5ioc2_msi_setup()
57 static void pnv_pci_init_p5ioc2_msis(struct pnv_phb *phb) in pnv_pci_init_p5ioc2_msis() argument
60 const __be32 *prop = of_get_property(phb->hose->dn, in pnv_pci_init_p5ioc2_msis()
68 if (of_device_is_compatible(phb->hose->dn, "ibm,p5ioc2-pcix")) in pnv_pci_init_p5ioc2_msis()
70 phb->msi_base = be32_to_cpup(prop); in pnv_pci_init_p5ioc2_msis()
72 if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { in pnv_pci_init_p5ioc2_msis()
74 phb->hose->global_number); in pnv_pci_init_p5ioc2_msis()
77 phb->msi_setup = pnv_pci_p5ioc2_msi_setup; in pnv_pci_init_p5ioc2_msis()
78 phb->msi32_support = 0; in pnv_pci_init_p5ioc2_msis()
80 count, phb->msi_base); in pnv_pci_init_p5ioc2_msis()
83 static void pnv_pci_init_p5ioc2_msis(struct pnv_phb *phb) { } in pnv_pci_init_p5ioc2_msis() argument
86 static void pnv_pci_p5ioc2_dma_dev_setup(struct pnv_phb *phb, in pnv_pci_p5ioc2_dma_dev_setup() argument
89 if (phb->p5ioc2.iommu_table.it_map == NULL) { in pnv_pci_p5ioc2_dma_dev_setup()
90 iommu_init_table(&phb->p5ioc2.iommu_table, phb->hose->node); in pnv_pci_p5ioc2_dma_dev_setup()
91 iommu_register_group(&phb->p5ioc2.iommu_table, in pnv_pci_p5ioc2_dma_dev_setup()
92 pci_domain_nr(phb->hose->bus), phb->opal_id); in pnv_pci_p5ioc2_dma_dev_setup()
95 set_iommu_table_base_and_group(&pdev->dev, &phb->p5ioc2.iommu_table); in pnv_pci_p5ioc2_dma_dev_setup()
101 struct pnv_phb *phb; in pnv_pci_init_p5ioc2_phb() local
125 phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0); in pnv_pci_init_p5ioc2_phb()
126 phb->hose = pcibios_alloc_controller(np); in pnv_pci_init_p5ioc2_phb()
127 if (!phb->hose) { in pnv_pci_init_p5ioc2_phb()
132 spin_lock_init(&phb->lock); in pnv_pci_init_p5ioc2_phb()
133 phb->hose->first_busno = 0; in pnv_pci_init_p5ioc2_phb()
134 phb->hose->last_busno = 0xff; in pnv_pci_init_p5ioc2_phb()
135 phb->hose->private_data = phb; in pnv_pci_init_p5ioc2_phb()
136 phb->hose->controller_ops = pnv_pci_controller_ops; in pnv_pci_init_p5ioc2_phb()
137 phb->hub_id = hub_id; in pnv_pci_init_p5ioc2_phb()
138 phb->opal_id = phb_id; in pnv_pci_init_p5ioc2_phb()
139 phb->type = PNV_PHB_P5IOC2; in pnv_pci_init_p5ioc2_phb()
140 phb->model = PNV_PHB_MODEL_P5IOC2; in pnv_pci_init_p5ioc2_phb()
142 phb->regs = of_iomap(np, 0); in pnv_pci_init_p5ioc2_phb()
144 if (phb->regs == NULL) in pnv_pci_init_p5ioc2_phb()
147 pr_devel(" P_BUID = 0x%08x\n", in_be32(phb->regs + 0x100)); in pnv_pci_init_p5ioc2_phb()
148 pr_devel(" P_IOSZ = 0x%08x\n", in_be32(phb->regs + 0x1b0)); in pnv_pci_init_p5ioc2_phb()
149 pr_devel(" P_IO_ST = 0x%08x\n", in_be32(phb->regs + 0x1e0)); in pnv_pci_init_p5ioc2_phb()
150 pr_devel(" P_MEM1_H = 0x%08x\n", in_be32(phb->regs + 0x1a0)); in pnv_pci_init_p5ioc2_phb()
151 pr_devel(" P_MEM1_L = 0x%08x\n", in_be32(phb->regs + 0x190)); in pnv_pci_init_p5ioc2_phb()
152 pr_devel(" P_MSZ1_L = 0x%08x\n", in_be32(phb->regs + 0x1c0)); in pnv_pci_init_p5ioc2_phb()
153 pr_devel(" P_MEM_ST = 0x%08x\n", in_be32(phb->regs + 0x1d0)); in pnv_pci_init_p5ioc2_phb()
154 pr_devel(" P_MEM2_H = 0x%08x\n", in_be32(phb->regs + 0x2c0)); in pnv_pci_init_p5ioc2_phb()
155 pr_devel(" P_MEM2_L = 0x%08x\n", in_be32(phb->regs + 0x2b0)); in pnv_pci_init_p5ioc2_phb()
156 pr_devel(" P_MSZ2_H = 0x%08x\n", in_be32(phb->regs + 0x2d0)); in pnv_pci_init_p5ioc2_phb()
157 pr_devel(" P_MSZ2_L = 0x%08x\n", in_be32(phb->regs + 0x2e0)); in pnv_pci_init_p5ioc2_phb()
162 pci_process_bridge_OF_ranges(phb->hose, np, primary); in pnv_pci_init_p5ioc2_phb()
165 phb->hose->ops = &pnv_pci_ops; in pnv_pci_init_p5ioc2_phb()
168 pnv_pci_init_p5ioc2_msis(phb); in pnv_pci_init_p5ioc2_phb()
171 phb->dma_dev_setup = pnv_pci_p5ioc2_dma_dev_setup; in pnv_pci_init_p5ioc2_phb()
172 pnv_pci_setup_iommu_table(&phb->p5ioc2.iommu_table, in pnv_pci_init_p5ioc2_phb()