Lines Matching refs:pe
50 static void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, in pe_level_printk() argument
62 if (pe->flags & PNV_IODA_PE_DEV) in pe_level_printk()
63 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); in pe_level_printk()
64 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) in pe_level_printk()
66 pci_domain_nr(pe->pbus), pe->pbus->number); in pe_level_printk()
68 else if (pe->flags & PNV_IODA_PE_VF) in pe_level_printk()
70 pci_domain_nr(pe->parent_dev->bus), in pe_level_printk()
71 (pe->rid & 0xff00) >> 8, in pe_level_printk()
72 PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); in pe_level_printk()
76 level, pfix, pe->pe_number, &vaf); in pe_level_printk()
81 #define pe_err(pe, fmt, ...) \ argument
82 pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__)
83 #define pe_warn(pe, fmt, ...) \ argument
84 pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__)
85 #define pe_info(pe, fmt, ...) \ argument
86 pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__)
146 unsigned long pe; in pnv_ioda_alloc_pe() local
149 pe = find_next_zero_bit(phb->ioda.pe_alloc, in pnv_ioda_alloc_pe()
151 if (pe >= phb->ioda.total_pe) in pnv_ioda_alloc_pe()
153 } while(test_and_set_bit(pe, phb->ioda.pe_alloc)); in pnv_ioda_alloc_pe()
155 phb->ioda.pe_array[pe].phb = phb; in pnv_ioda_alloc_pe()
156 phb->ioda.pe_array[pe].pe_number = pe; in pnv_ioda_alloc_pe()
157 return pe; in pnv_ioda_alloc_pe()
160 static void pnv_ioda_free_pe(struct pnv_phb *phb, int pe) in pnv_ioda_free_pe() argument
162 WARN_ON(phb->ioda.pe_array[pe].pdev); in pnv_ioda_free_pe()
164 memset(&phb->ioda.pe_array[pe], 0, sizeof(struct pnv_ioda_pe)); in pnv_ioda_free_pe()
165 clear_bit(pe, phb->ioda.pe_alloc); in pnv_ioda_free_pe()
257 struct pnv_ioda_pe *master_pe, *pe; in pnv_ioda2_pick_m64_pe() local
338 pe = &phb->ioda.pe_array[i]; in pnv_ioda2_pick_m64_pe()
341 pe->flags |= PNV_IODA_PE_MASTER; in pnv_ioda2_pick_m64_pe()
342 INIT_LIST_HEAD(&pe->slaves); in pnv_ioda2_pick_m64_pe()
343 master_pe = pe; in pnv_ioda2_pick_m64_pe()
345 pe->flags |= PNV_IODA_PE_SLAVE; in pnv_ioda2_pick_m64_pe()
346 pe->master = master_pe; in pnv_ioda2_pick_m64_pe()
347 list_add_tail(&pe->list, &master_pe->slaves); in pnv_ioda2_pick_m64_pe()
404 struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; in pnv_ioda_freeze_pe() local
409 if (pe->flags & PNV_IODA_PE_SLAVE) { in pnv_ioda_freeze_pe()
410 pe = pe->master; in pnv_ioda_freeze_pe()
411 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) in pnv_ioda_freeze_pe()
414 pe_no = pe->pe_number; in pnv_ioda_freeze_pe()
428 if (!(pe->flags & PNV_IODA_PE_MASTER)) in pnv_ioda_freeze_pe()
431 list_for_each_entry(slave, &pe->slaves, list) { in pnv_ioda_freeze_pe()
444 struct pnv_ioda_pe *pe, *slave; in pnv_ioda_unfreeze_pe() local
448 pe = &phb->ioda.pe_array[pe_no]; in pnv_ioda_unfreeze_pe()
449 if (pe->flags & PNV_IODA_PE_SLAVE) { in pnv_ioda_unfreeze_pe()
450 pe = pe->master; in pnv_ioda_unfreeze_pe()
451 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); in pnv_ioda_unfreeze_pe()
452 pe_no = pe->pe_number; in pnv_ioda_unfreeze_pe()
463 if (!(pe->flags & PNV_IODA_PE_MASTER)) in pnv_ioda_unfreeze_pe()
467 list_for_each_entry(slave, &pe->slaves, list) { in pnv_ioda_unfreeze_pe()
484 struct pnv_ioda_pe *slave, *pe; in pnv_ioda_get_pe_state() local
497 pe = &phb->ioda.pe_array[pe_no]; in pnv_ioda_get_pe_state()
498 if (pe->flags & PNV_IODA_PE_SLAVE) { in pnv_ioda_get_pe_state()
499 pe = pe->master; in pnv_ioda_get_pe_state()
500 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); in pnv_ioda_get_pe_state()
501 pe_no = pe->pe_number; in pnv_ioda_get_pe_state()
516 if (!(pe->flags & PNV_IODA_PE_MASTER)) in pnv_ioda_get_pe_state()
519 list_for_each_entry(slave, &pe->slaves, list) { in pnv_ioda_get_pe_state()
600 struct pnv_ioda_pe *pe, in pnv_ioda_set_peltv() argument
612 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, in pnv_ioda_set_peltv()
614 if (pe->flags & PNV_IODA_PE_MASTER) { in pnv_ioda_set_peltv()
615 list_for_each_entry(slave, &pe->slaves, list) in pnv_ioda_set_peltv()
628 ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); in pnv_ioda_set_peltv()
633 if (pe->flags & PNV_IODA_PE_MASTER) { in pnv_ioda_set_peltv()
634 list_for_each_entry(slave, &pe->slaves, list) { in pnv_ioda_set_peltv()
635 ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); in pnv_ioda_set_peltv()
641 if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) in pnv_ioda_set_peltv()
642 pdev = pe->pbus->self; in pnv_ioda_set_peltv()
643 else if (pe->flags & PNV_IODA_PE_DEV) in pnv_ioda_set_peltv()
644 pdev = pe->pdev->bus->self; in pnv_ioda_set_peltv()
646 else if (pe->flags & PNV_IODA_PE_VF) in pnv_ioda_set_peltv()
647 pdev = pe->parent_dev->bus->self; in pnv_ioda_set_peltv()
655 ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); in pnv_ioda_set_peltv()
667 static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) in pnv_ioda_deconfigure_pe() argument
675 if (pe->pbus) { in pnv_ioda_deconfigure_pe()
680 parent = pe->pbus->self; in pnv_ioda_deconfigure_pe()
681 if (pe->flags & PNV_IODA_PE_BUS_ALL) in pnv_ioda_deconfigure_pe()
682 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; in pnv_ioda_deconfigure_pe()
694 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", in pnv_ioda_deconfigure_pe()
699 rid_end = pe->rid + (count << 8); in pnv_ioda_deconfigure_pe()
701 if (pe->flags & PNV_IODA_PE_VF) in pnv_ioda_deconfigure_pe()
702 parent = pe->parent_dev; in pnv_ioda_deconfigure_pe()
704 parent = pe->pdev->bus->self; in pnv_ioda_deconfigure_pe()
708 rid_end = pe->rid + 1; in pnv_ioda_deconfigure_pe()
712 for (rid = pe->rid; rid < rid_end; rid++) in pnv_ioda_deconfigure_pe()
720 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); in pnv_ioda_deconfigure_pe()
726 opal_pci_eeh_freeze_set(phb->opal_id, pe->pe_number, in pnv_ioda_deconfigure_pe()
730 rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, in pnv_ioda_deconfigure_pe()
731 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); in pnv_ioda_deconfigure_pe()
733 pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc); in pnv_ioda_deconfigure_pe()
734 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, in pnv_ioda_deconfigure_pe()
737 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); in pnv_ioda_deconfigure_pe()
739 pe->pbus = NULL; in pnv_ioda_deconfigure_pe()
740 pe->pdev = NULL; in pnv_ioda_deconfigure_pe()
741 pe->parent_dev = NULL; in pnv_ioda_deconfigure_pe()
747 static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) in pnv_ioda_configure_pe() argument
754 if (pe->pbus) { in pnv_ioda_configure_pe()
759 parent = pe->pbus->self; in pnv_ioda_configure_pe()
760 if (pe->flags & PNV_IODA_PE_BUS_ALL) in pnv_ioda_configure_pe()
761 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; in pnv_ioda_configure_pe()
773 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", in pnv_ioda_configure_pe()
778 rid_end = pe->rid + (count << 8); in pnv_ioda_configure_pe()
781 if (pe->flags & PNV_IODA_PE_VF) in pnv_ioda_configure_pe()
782 parent = pe->parent_dev; in pnv_ioda_configure_pe()
785 parent = pe->pdev->bus->self; in pnv_ioda_configure_pe()
789 rid_end = pe->rid + 1; in pnv_ioda_configure_pe()
798 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, in pnv_ioda_configure_pe()
801 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); in pnv_ioda_configure_pe()
806 pnv_ioda_set_peltv(phb, pe, true); in pnv_ioda_configure_pe()
809 for (rid = pe->rid; rid < rid_end; rid++) in pnv_ioda_configure_pe()
810 phb->ioda.pe_rmap[rid] = pe->pe_number; in pnv_ioda_configure_pe()
814 pe->mve_number = 0; in pnv_ioda_configure_pe()
818 pe->mve_number = pe->pe_number; in pnv_ioda_configure_pe()
819 rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); in pnv_ioda_configure_pe()
821 pe_err(pe, "OPAL error %ld setting up MVE %d\n", in pnv_ioda_configure_pe()
822 rc, pe->mve_number); in pnv_ioda_configure_pe()
823 pe->mve_number = -1; in pnv_ioda_configure_pe()
826 pe->mve_number, OPAL_ENABLE_MVE); in pnv_ioda_configure_pe()
828 pe_err(pe, "OPAL error %ld enabling MVE %d\n", in pnv_ioda_configure_pe()
829 rc, pe->mve_number); in pnv_ioda_configure_pe()
830 pe->mve_number = -1; in pnv_ioda_configure_pe()
839 struct pnv_ioda_pe *pe) in pnv_ioda_link_pe_by_weight() argument
844 if (lpe->dma_weight < pe->dma_weight) { in pnv_ioda_link_pe_by_weight()
845 list_add_tail(&pe->dma_link, &lpe->dma_link); in pnv_ioda_link_pe_by_weight()
849 list_add_tail(&pe->dma_link, &phb->ioda.pe_dma_list); in pnv_ioda_link_pe_by_weight()
954 struct pnv_ioda_pe *pe;
983 pe = &phb->ioda.pe_array[pe_num];
987 pe->pdev = dev;
988 pe->pbus = NULL;
989 pe->tce32_seg = -1;
990 pe->mve_number = -1;
991 pe->rid = dev->bus->number << 8 | pdn->devfn;
993 pe_info(pe, "Associated device to PE\n");
995 if (pnv_ioda_configure_pe(phb, pe)) {
1000 pe->pdev = NULL;
1006 pe->dma_weight = pnv_ioda_dma_weight(dev);
1007 if (pe->dma_weight != 0) {
1008 phb->ioda.dma_weight += pe->dma_weight;
1013 pnv_ioda_link_pe_by_weight(phb, pe);
1015 return pe;
1019 static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) in pnv_ioda_setup_same_PE() argument
1031 pdn->pe_number = pe->pe_number; in pnv_ioda_setup_same_PE()
1032 pe->dma_weight += pnv_ioda_dma_weight(dev); in pnv_ioda_setup_same_PE()
1033 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) in pnv_ioda_setup_same_PE()
1034 pnv_ioda_setup_same_PE(dev->subordinate, pe); in pnv_ioda_setup_same_PE()
1048 struct pnv_ioda_pe *pe; in pnv_ioda_setup_bus_PE() local
1065 pe = &phb->ioda.pe_array[pe_num]; in pnv_ioda_setup_bus_PE()
1066 pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); in pnv_ioda_setup_bus_PE()
1067 pe->pbus = bus; in pnv_ioda_setup_bus_PE()
1068 pe->pdev = NULL; in pnv_ioda_setup_bus_PE()
1069 pe->tce32_seg = -1; in pnv_ioda_setup_bus_PE()
1070 pe->mve_number = -1; in pnv_ioda_setup_bus_PE()
1071 pe->rid = bus->busn_res.start << 8; in pnv_ioda_setup_bus_PE()
1072 pe->dma_weight = 0; in pnv_ioda_setup_bus_PE()
1075 pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n", in pnv_ioda_setup_bus_PE()
1078 pe_info(pe, "Secondary bus %d associated with PE#%d\n", in pnv_ioda_setup_bus_PE()
1081 if (pnv_ioda_configure_pe(phb, pe)) { in pnv_ioda_setup_bus_PE()
1085 pe->pbus = NULL; in pnv_ioda_setup_bus_PE()
1089 pe->tce32_table = kzalloc_node(sizeof(struct iommu_table), in pnv_ioda_setup_bus_PE()
1091 pe->tce32_table->data = pe; in pnv_ioda_setup_bus_PE()
1094 pnv_ioda_setup_same_PE(bus, pe); in pnv_ioda_setup_bus_PE()
1097 list_add_tail(&pe->list, &phb->ioda.pe_list); in pnv_ioda_setup_bus_PE()
1102 if (pe->dma_weight != 0) { in pnv_ioda_setup_bus_PE()
1103 phb->ioda.dma_weight += pe->dma_weight; in pnv_ioda_setup_bus_PE()
1108 pnv_ioda_link_pe_by_weight(phb, pe); in pnv_ioda_setup_bus_PE()
1286 static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe) in pnv_pci_ioda2_release_dma_pe() argument
1298 tbl = pe->tce32_table; in pnv_pci_ioda2_release_dma_pe()
1301 opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, in pnv_pci_ioda2_release_dma_pe()
1302 pe->pe_number << 1, 1, __pa(addr), in pnv_pci_ioda2_release_dma_pe()
1305 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, in pnv_pci_ioda2_release_dma_pe()
1306 pe->pe_number, in pnv_pci_ioda2_release_dma_pe()
1307 (pe->pe_number << 1) + 1, in pnv_pci_ioda2_release_dma_pe()
1308 pe->tce_bypass_base, in pnv_pci_ioda2_release_dma_pe()
1311 pe_warn(pe, "OPAL error %ld release DMA window\n", rc); in pnv_pci_ioda2_release_dma_pe()
1315 pe->tce32_table = NULL; in pnv_pci_ioda2_release_dma_pe()
1323 struct pnv_ioda_pe *pe, *pe_n; in pnv_ioda_release_vf_PE() local
1365 list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { in pnv_ioda_release_vf_PE()
1366 if (pe->parent_dev != pdev) in pnv_ioda_release_vf_PE()
1369 pnv_pci_ioda2_release_dma_pe(pdev, pe); in pnv_ioda_release_vf_PE()
1373 list_del(&pe->list); in pnv_ioda_release_vf_PE()
1376 pnv_ioda_deconfigure_pe(phb, pe); in pnv_ioda_release_vf_PE()
1378 pnv_ioda_free_pe(phb, pe->pe_number); in pnv_ioda_release_vf_PE()
1415 struct pnv_ioda_pe *pe);
1421 struct pnv_ioda_pe *pe; in pnv_ioda_setup_vf_PE() local
1439 pe = &phb->ioda.pe_array[pe_num]; in pnv_ioda_setup_vf_PE()
1440 pe->pe_number = pe_num; in pnv_ioda_setup_vf_PE()
1441 pe->phb = phb; in pnv_ioda_setup_vf_PE()
1442 pe->flags = PNV_IODA_PE_VF; in pnv_ioda_setup_vf_PE()
1443 pe->pbus = NULL; in pnv_ioda_setup_vf_PE()
1444 pe->parent_dev = pdev; in pnv_ioda_setup_vf_PE()
1445 pe->tce32_seg = -1; in pnv_ioda_setup_vf_PE()
1446 pe->mve_number = -1; in pnv_ioda_setup_vf_PE()
1447 pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) | in pnv_ioda_setup_vf_PE()
1450 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%d\n", in pnv_ioda_setup_vf_PE()
1455 if (pnv_ioda_configure_pe(phb, pe)) { in pnv_ioda_setup_vf_PE()
1459 pe->pdev = NULL; in pnv_ioda_setup_vf_PE()
1463 pe->tce32_table = kzalloc_node(sizeof(struct iommu_table), in pnv_ioda_setup_vf_PE()
1465 pe->tce32_table->data = pe; in pnv_ioda_setup_vf_PE()
1469 list_add_tail(&pe->list, &phb->ioda.pe_list); in pnv_ioda_setup_vf_PE()
1472 pnv_pci_ioda2_setup_dma_pe(phb, pe); in pnv_ioda_setup_vf_PE()
1589 struct pnv_ioda_pe *pe; in pnv_pci_ioda_dma_dev_setup() local
1599 pe = &phb->ioda.pe_array[pdn->pe_number]; in pnv_pci_ioda_dma_dev_setup()
1601 set_iommu_table_base_and_group(&pdev->dev, pe->tce32_table); in pnv_pci_ioda_dma_dev_setup()
1608 struct pnv_ioda_pe *pe; in pnv_pci_ioda_dma_set_mask() local
1615 pe = &phb->ioda.pe_array[pdn->pe_number]; in pnv_pci_ioda_dma_set_mask()
1616 if (pe->tce_bypass_enabled) { in pnv_pci_ioda_dma_set_mask()
1617 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; in pnv_pci_ioda_dma_set_mask()
1624 set_dma_offset(&pdev->dev, pe->tce_bypass_base); in pnv_pci_ioda_dma_set_mask()
1628 set_iommu_table_base(&pdev->dev, pe->tce32_table); in pnv_pci_ioda_dma_set_mask()
1638 struct pnv_ioda_pe *pe; in pnv_pci_ioda_dma_get_required_mask() local
1644 pe = &phb->ioda.pe_array[pdn->pe_number]; in pnv_pci_ioda_dma_get_required_mask()
1645 if (!pe->tce_bypass_enabled) in pnv_pci_ioda_dma_get_required_mask()
1649 end = pe->tce_bypass_base + memblock_end_of_DRAM(); in pnv_pci_ioda_dma_get_required_mask()
1656 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, in pnv_ioda_setup_bus_dma() argument
1665 pe->tce32_table); in pnv_ioda_setup_bus_dma()
1667 set_iommu_table_base(&dev->dev, pe->tce32_table); in pnv_ioda_setup_bus_dma()
1670 pnv_ioda_setup_bus_dma(pe, dev->subordinate, in pnv_ioda_setup_bus_dma()
1675 static void pnv_pci_ioda1_tce_invalidate(struct pnv_ioda_pe *pe, in pnv_pci_ioda1_tce_invalidate() argument
1680 (__be64 __iomem *)pe->tce_inval_reg_phys : in pnv_pci_ioda1_tce_invalidate()
1722 static void pnv_pci_ioda2_tce_invalidate(struct pnv_ioda_pe *pe, in pnv_pci_ioda2_tce_invalidate() argument
1728 (__be64 __iomem *)pe->tce_inval_reg_phys : in pnv_pci_ioda2_tce_invalidate()
1734 start |= (pe->pe_number & 0xFF); in pnv_pci_ioda2_tce_invalidate()
1757 struct pnv_ioda_pe *pe = tbl->data; in pnv_pci_ioda_tce_invalidate() local
1758 struct pnv_phb *phb = pe->phb; in pnv_pci_ioda_tce_invalidate()
1761 pnv_pci_ioda1_tce_invalidate(pe, tbl, startp, endp, rm); in pnv_pci_ioda_tce_invalidate()
1763 pnv_pci_ioda2_tce_invalidate(pe, tbl, startp, endp, rm); in pnv_pci_ioda_tce_invalidate()
1767 struct pnv_ioda_pe *pe, unsigned int base, in pnv_pci_ioda_setup_dma_pe() argument
1783 if (WARN_ON(pe->tce32_seg >= 0)) in pnv_pci_ioda_setup_dma_pe()
1787 pe->tce32_seg = base; in pnv_pci_ioda_setup_dma_pe()
1788 pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", in pnv_pci_ioda_setup_dma_pe()
1799 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); in pnv_pci_ioda_setup_dma_pe()
1808 pe->pe_number, in pnv_pci_ioda_setup_dma_pe()
1813 pe_err(pe, " Failed to configure 32-bit TCE table," in pnv_pci_ioda_setup_dma_pe()
1820 tbl = pe->tce32_table; in pnv_pci_ioda_setup_dma_pe()
1832 pe->tce_inval_reg_phys = be64_to_cpup(swinvp); in pnv_pci_ioda_setup_dma_pe()
1833 tbl->it_index = (unsigned long)ioremap(pe->tce_inval_reg_phys, in pnv_pci_ioda_setup_dma_pe()
1841 if (pe->flags & PNV_IODA_PE_DEV) { in pnv_pci_ioda_setup_dma_pe()
1843 pe->pe_number); in pnv_pci_ioda_setup_dma_pe()
1844 set_iommu_table_base_and_group(&pe->pdev->dev, tbl); in pnv_pci_ioda_setup_dma_pe()
1845 } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) { in pnv_pci_ioda_setup_dma_pe()
1847 pe->pe_number); in pnv_pci_ioda_setup_dma_pe()
1848 pnv_ioda_setup_bus_dma(pe, pe->pbus, true); in pnv_pci_ioda_setup_dma_pe()
1849 } else if (pe->flags & PNV_IODA_PE_VF) { in pnv_pci_ioda_setup_dma_pe()
1851 pe->pe_number); in pnv_pci_ioda_setup_dma_pe()
1857 if (pe->tce32_seg >= 0) in pnv_pci_ioda_setup_dma_pe()
1858 pe->tce32_seg = -1; in pnv_pci_ioda_setup_dma_pe()
1865 struct pnv_ioda_pe *pe = tbl->data; in pnv_pci_ioda2_set_bypass() local
1866 uint16_t window_id = (pe->pe_number << 1 ) + 1; in pnv_pci_ioda2_set_bypass()
1869 pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); in pnv_pci_ioda2_set_bypass()
1874 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, in pnv_pci_ioda2_set_bypass()
1875 pe->pe_number, in pnv_pci_ioda2_set_bypass()
1877 pe->tce_bypass_base, in pnv_pci_ioda2_set_bypass()
1880 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, in pnv_pci_ioda2_set_bypass()
1881 pe->pe_number, in pnv_pci_ioda2_set_bypass()
1883 pe->tce_bypass_base, in pnv_pci_ioda2_set_bypass()
1892 if (pe->pdev) in pnv_pci_ioda2_set_bypass()
1893 set_iommu_table_base(&pe->pdev->dev, tbl); in pnv_pci_ioda2_set_bypass()
1895 pnv_ioda_setup_bus_dma(pe, pe->pbus, false); in pnv_pci_ioda2_set_bypass()
1898 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); in pnv_pci_ioda2_set_bypass()
1900 pe->tce_bypass_enabled = enable; in pnv_pci_ioda2_set_bypass()
1904 struct pnv_ioda_pe *pe) in pnv_pci_ioda2_setup_bypass_pe() argument
1907 pe->tce_bypass_base = 1ull << 59; in pnv_pci_ioda2_setup_bypass_pe()
1910 pe->tce32_table->set_bypass = pnv_pci_ioda2_set_bypass; in pnv_pci_ioda2_setup_bypass_pe()
1913 pnv_pci_ioda2_set_bypass(pe->tce32_table, true); in pnv_pci_ioda2_setup_bypass_pe()
1917 struct pnv_ioda_pe *pe) in pnv_pci_ioda2_setup_dma_pe() argument
1927 if (WARN_ON(pe->tce32_seg >= 0)) in pnv_pci_ioda2_setup_dma_pe()
1931 pe->tce32_seg = 0; in pnv_pci_ioda2_setup_dma_pe()
1934 pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", in pnv_pci_ioda2_setup_dma_pe()
1941 pe_err(pe, "Failed to allocate a 32-bit TCE memory\n"); in pnv_pci_ioda2_setup_dma_pe()
1951 rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, in pnv_pci_ioda2_setup_dma_pe()
1952 pe->pe_number << 1, 1, __pa(addr), in pnv_pci_ioda2_setup_dma_pe()
1955 pe_err(pe, "Failed to configure 32-bit TCE table," in pnv_pci_ioda2_setup_dma_pe()
1961 tbl = pe->tce32_table; in pnv_pci_ioda2_setup_dma_pe()
1973 pe->tce_inval_reg_phys = be64_to_cpup(swinvp); in pnv_pci_ioda2_setup_dma_pe()
1974 tbl->it_index = (unsigned long)ioremap(pe->tce_inval_reg_phys, in pnv_pci_ioda2_setup_dma_pe()
1980 if (pe->flags & PNV_IODA_PE_DEV) { in pnv_pci_ioda2_setup_dma_pe()
1982 pe->pe_number); in pnv_pci_ioda2_setup_dma_pe()
1983 set_iommu_table_base_and_group(&pe->pdev->dev, tbl); in pnv_pci_ioda2_setup_dma_pe()
1984 } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) { in pnv_pci_ioda2_setup_dma_pe()
1986 pe->pe_number); in pnv_pci_ioda2_setup_dma_pe()
1987 pnv_ioda_setup_bus_dma(pe, pe->pbus, true); in pnv_pci_ioda2_setup_dma_pe()
1988 } else if (pe->flags & PNV_IODA_PE_VF) { in pnv_pci_ioda2_setup_dma_pe()
1990 pe->pe_number); in pnv_pci_ioda2_setup_dma_pe()
1995 pnv_pci_ioda2_setup_bypass_pe(phb, pe); in pnv_pci_ioda2_setup_dma_pe()
1999 if (pe->tce32_seg >= 0) in pnv_pci_ioda2_setup_dma_pe()
2000 pe->tce32_seg = -1; in pnv_pci_ioda2_setup_dma_pe()
2009 struct pnv_ioda_pe *pe; in pnv_ioda_setup_dma() local
2034 list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) { in pnv_ioda_setup_dma()
2035 if (!pe->dma_weight) in pnv_ioda_setup_dma()
2038 pe_warn(pe, "No DMA32 resources available\n"); in pnv_ioda_setup_dma()
2043 segs += ((pe->dma_weight * residual) + (tw / 2)) / tw; in pnv_ioda_setup_dma()
2054 pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n", in pnv_ioda_setup_dma()
2055 pe->dma_weight, segs); in pnv_ioda_setup_dma()
2056 pnv_pci_ioda_setup_dma_pe(phb, pe, base, segs); in pnv_ioda_setup_dma()
2058 pe_info(pe, "Assign DMA32 space\n"); in pnv_ioda_setup_dma()
2060 pnv_pci_ioda2_setup_dma_pe(phb, pe); in pnv_ioda_setup_dma()
2120 struct pnv_ioda_pe *pe; in pnv_phb_to_cxl_mode() local
2123 pe = pnv_ioda_get_pe(dev); in pnv_phb_to_cxl_mode()
2124 if (!pe) in pnv_phb_to_cxl_mode()
2127 pe_info(pe, "Switching PHB to CXL\n"); in pnv_phb_to_cxl_mode()
2129 rc = opal_pci_set_phb_cxl_mode(phb->opal_id, mode, pe->pe_number); in pnv_phb_to_cxl_mode()
2236 struct pnv_ioda_pe *pe; in pnv_cxl_ioda_msi_setup() local
2239 if (!(pe = pnv_ioda_get_pe(dev))) in pnv_cxl_ioda_msi_setup()
2243 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); in pnv_cxl_ioda_msi_setup()
2245 pe_warn(pe, "%s: OPAL error %d setting msi_base 0x%x " in pnv_cxl_ioda_msi_setup()
2261 struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); in pnv_pci_ioda_msi_setup() local
2267 if (pe == NULL) in pnv_pci_ioda_msi_setup()
2271 if (pe->mve_number < 0) in pnv_pci_ioda_msi_setup()
2279 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); in pnv_pci_ioda_msi_setup()
2289 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, in pnv_pci_ioda_msi_setup()
2301 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, in pnv_pci_ioda_msi_setup()
2318 msg->address_hi, msg->address_lo, data, pe->pe_number); in pnv_pci_ioda_msi_setup()
2425 struct pnv_ioda_pe *pe) in pnv_ioda_setup_pe_seg() argument
2438 BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); in pnv_ioda_setup_pe_seg()
2440 pci_bus_for_each_resource(pe->pbus, res, i) { in pnv_ioda_setup_pe_seg()
2452 phb->ioda.io_segmap[index] = pe->pe_number; in pnv_ioda_setup_pe_seg()
2454 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); in pnv_ioda_setup_pe_seg()
2458 __func__, rc, index, pe->pe_number); in pnv_ioda_setup_pe_seg()
2477 phb->ioda.m32_segmap[index] = pe->pe_number; in pnv_ioda_setup_pe_seg()
2479 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); in pnv_ioda_setup_pe_seg()
2483 __func__, rc, index, pe->pe_number); in pnv_ioda_setup_pe_seg()
2498 struct pnv_ioda_pe *pe; in pnv_pci_ioda_setup_seg() local
2502 list_for_each_entry(pe, &phb->ioda.pe_list, list) { in pnv_pci_ioda_setup_seg()
2503 pnv_ioda_setup_pe_seg(hose, pe); in pnv_pci_ioda_setup_seg()