286 static void set_pm_event(u32 ctr, int event, u32 unit_mask)  in set_pm_event()  argument
295 		pm_regs.pm07_cntrl[ctr] = CBE_COUNT_ALL_CYCLES;  in set_pm_event()
296 		p = &(pm_signal[ctr]);  in set_pm_event()
303 		pm_regs.pm07_cntrl[ctr] = 0;  in set_pm_event()
313 	p = &(pm_signal[ctr]);  in set_pm_event()
319 	pm_regs.pm07_cntrl[ctr] = 0;  in set_pm_event()
320 	pm_regs.pm07_cntrl[ctr] |= PM07_CTR_COUNT_CYCLES(count_cycles);  in set_pm_event()
321 	pm_regs.pm07_cntrl[ctr] |= PM07_CTR_POLARITY(polarity);  in set_pm_event()
322 	pm_regs.pm07_cntrl[ctr] |= PM07_CTR_INPUT_CONTROL(input_control);  in set_pm_event()
347 		pm_regs.pm07_cntrl[ctr] |= PM07_CTR_INPUT_MUX(signal_bit);  in set_pm_event()
349 		pm_regs.pm07_cntrl[ctr] = 0;  in set_pm_event()
428 static inline void enable_ctr(u32 cpu, u32 ctr, u32 *pm07_cntrl)  in enable_ctr()  argument
431 	pm07_cntrl[ctr] |= CBE_PM_CTR_ENABLE;  in enable_ctr()
432 	cbe_write_pm07_control(cpu, ctr, pm07_cntrl[ctr]);  in enable_ctr()
565 static int cell_reg_setup_spu_cycles(struct op_counter_config *ctr,  in cell_reg_setup_spu_cycles()  argument
568 	spu_cycle_reset = ctr[0].count;  in cell_reg_setup_spu_cycles()
689 static int cell_reg_setup_spu_events(struct op_counter_config *ctr,  in cell_reg_setup_spu_events()  argument
744 	set_pm_event(0, ctr[0].event, ctr[0].unit_mask);  in cell_reg_setup_spu_events()
746 	reset_value[0] = 0xFFFFFFFF - ctr[0].count;  in cell_reg_setup_spu_events()
758 static int cell_reg_setup_ppu(struct op_counter_config *ctr,  in cell_reg_setup_ppu()  argument
779 		pmc_cntrl[0][i].evnts = ctr[i].event;  in cell_reg_setup_ppu()
780 		pmc_cntrl[0][i].masks = ctr[i].unit_mask;  in cell_reg_setup_ppu()
781 		pmc_cntrl[0][i].enabled = ctr[i].enabled;  in cell_reg_setup_ppu()
793 		if ((ctr[i].event >= 2100) && (ctr[i].event <= 2111))  in cell_reg_setup_ppu()
794 			pmc_cntrl[1][i].evnts = ctr[i].event + 19;  in cell_reg_setup_ppu()
795 		else if (ctr[i].event == 2203)  in cell_reg_setup_ppu()
796 			pmc_cntrl[1][i].evnts = ctr[i].event;  in cell_reg_setup_ppu()
797 		else if ((ctr[i].event >= 2200) && (ctr[i].event <= 2215))  in cell_reg_setup_ppu()
798 			pmc_cntrl[1][i].evnts = ctr[i].event + 16;  in cell_reg_setup_ppu()
800 			pmc_cntrl[1][i].evnts = ctr[i].event;  in cell_reg_setup_ppu()
802 		pmc_cntrl[1][i].masks = ctr[i].unit_mask;  in cell_reg_setup_ppu()
803 		pmc_cntrl[1][i].enabled = ctr[i].enabled;  in cell_reg_setup_ppu()
821 			reset_value[i] = 0xFFFFFFFF - ctr[i].count;  in cell_reg_setup_ppu()
842 static int cell_reg_setup(struct op_counter_config *ctr,  in cell_reg_setup()  argument
874 	if (ctr[0].event == SPU_CYCLES_EVENT_NUM) {  in cell_reg_setup()
876 		ret = cell_reg_setup_spu_cycles(ctr, sys, num_ctrs);  in cell_reg_setup()
877 	} else if ((ctr[0].event >= SPU_EVENT_NUM_START) &&  in cell_reg_setup()
878 		   (ctr[0].event <= SPU_EVENT_NUM_STOP)) {  in cell_reg_setup()
880 		spu_cycle_reset = ctr[0].count;  in cell_reg_setup()
888 		cell_reg_setup_spu_events(ctr, sys, num_ctrs);  in cell_reg_setup()
891 		ret = cell_reg_setup_ppu(ctr, sys, num_ctrs);  in cell_reg_setup()
1249 static int cell_global_start_spu_cycles(struct op_counter_config *ctr)  in cell_global_start_spu_cycles()  argument
1339 static int cell_global_start_spu_events(struct op_counter_config *ctr)  in cell_global_start_spu_events()  argument
1402 static int cell_global_start_ppu(struct op_counter_config *ctr)  in cell_global_start_ppu()  argument
1448 static int cell_global_start(struct op_counter_config *ctr)  in cell_global_start()  argument
1451 		return cell_global_start_spu_cycles(ctr);  in cell_global_start()
1453 		return cell_global_start_spu_events(ctr);  in cell_global_start()
1455 		return cell_global_start_ppu(ctr);  in cell_global_start()
1487 				      struct op_counter_config *ctr)  in cell_handle_interrupt_spu()  argument
1521 		    && ctr[0].enabled)  in cell_handle_interrupt_spu()
1605 				      struct op_counter_config *ctr)  in cell_handle_interrupt_ppu()  argument
1646 			    && ctr[i].enabled) {  in cell_handle_interrupt_ppu()
1678 				  struct op_counter_config *ctr)  in cell_handle_interrupt()  argument
1681 		cell_handle_interrupt_ppu(regs, ctr);  in cell_handle_interrupt()
1683 		cell_handle_interrupt_spu(regs, ctr);  in cell_handle_interrupt()