Lines Matching refs:r8
95 lwz r8, HSTATE_PMC5(r13)
101 mtspr SPRN_PMC5, r8
113 ld r8, HSTATE_MMCR2(r13)
115 mtspr SPRN_MMCR2, r8
142 ld r8, 112+PPC_LR_STKOFF(r1)
157 mtsrr0 r8
163 11: mtspr SPRN_HSRR0, r8
169 14: mtspr SPRN_HSRR0, r8
188 ld r8,VCORE_LPCR(r5)
189 mtspr SPRN_LPCR,r8
492 22: ld r8,VCORE_TB_OFFSET(r5)
493 cmpdi r8,0
496 add r8,r8,r6
497 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
503 addis r8,r8,0x100 /* if so, increment upper 40 bits */
504 mtspr SPRN_TBU40,r8
515 ld r8, VCORE_DPDES(r5)
516 mtspr SPRN_DPDES, r8
533 1: ld r8,VCPU_SLB_E(r6)
535 slbmte r9,r8
557 ld r8,VCPU_SPURR(r4)
559 mtspr SPRN_SPURR,r8
626 ld r8, VCPU_AMR_TM(r4)
631 mtspr SPRN_AMR, r8
697 lwz r8, VCPU_PMC + 16(r4)
703 mtspr SPRN_PMC5, r8
709 ld r8, VCPU_SDAR(r4)
713 mtspr SPRN_SDAR, r8
718 lwz r8, VCPU_PMC + 28(r4)
723 mtspr SPRN_SPMC2, r8
760 mfmsr r8
762 rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG
763 mtmsrd r8
775 ld r8, VCPU_TAR(r4)
779 mtspr SPRN_TAR, r8
784 ld r8, VCPU_EBBHR(r4)
785 mtspr SPRN_EBBHR, r8
789 ld r8, VCPU_TACR(r4)
793 mtspr SPRN_TACR, r8
797 ld r8, VCPU_WORT(r4)
801 mtspr SPRN_WORT, r8
807 ld r8,VCPU_DEC_EXPIRES(r4)
811 add r8,r8,r6
813 subf r3,r7,r8
820 ld r8, VCPU_SPRG3(r4)
824 mtspr SPRN_SPRG3, r8
863 ld r8,VCORE_LPCR(r5)
864 mtspr SPRN_LPCR,r8
896 andi. r8, r11, MSR_EE
897 mfspr r8, SPRN_LPCR
899 rldimi r8, r0, LPCR_MER_SH, 63 - LPCR_MER_SH
900 mtspr SPRN_LPCR, r8
961 ld r8, VCPU_GPR(R8)(r4)
1042 std r8, VCPU_GPR(R8)(r9)
1090 ld r8, VCPU_GPR(R8)(r9)
1195 1: slbmfee r8,r6
1196 andis. r0,r8,SLB_ESID_V@h
1198 add r8,r8,r6 /* put index in */
1200 std r8,VCPU_SLB_E(r7)
1214 ld r8,VCPU_SPURR(r9)
1218 subf r6,r8,r6
1258 mfspr r8, SPRN_EBBHR
1259 std r8, VCPU_EBBHR(r9)
1263 mfspr r8, SPRN_TACR
1267 std r8, VCPU_TACR(r9)
1271 mfspr r8, SPRN_WORT
1275 std r8, VCPU_WORT(r9)
1301 mfspr r8, SPRN_DSCR
1303 std r8, VCPU_DSCR(r9)
1345 mfmsr r8
1347 rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG
1348 mtmsrd r8
1410 mfspr r8, SPRN_AMR
1415 std r8, VCPU_AMR_TM(r9)
1445 ld r8, VCPU_VPA(r9) /* do they have a VPA? */
1446 cmpdi r8, 0
1449 LWZX_BE r3, r8, r4
1451 STWX_BE r3, r8, r4
1491 lbz r7, LPPACA_PMCINUSE(r8)
1498 mfspr r8, SPRN_SDAR
1506 std r8, VCPU_SDAR(r9)
1512 mfspr r8, SPRN_PMC6
1518 stw r8, VCPU_PMC + 20(r9)
1523 mfspr r8, SPRN_MMCRS
1527 std r8, VCPU_MMCR + 32(r9)
1568 li r8,LPID_RSVD /* switch to reserved LPID */
1569 mtspr SPRN_LPID,r8
1580 li r8, 0
1581 mtspr SPRN_DPDES, r8
1585 ld r8,VCORE_TB_OFFSET(r5)
1586 cmpdi r8,0
1589 subf r8,r8,r6
1590 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
1596 addis r8,r8,0x100 /* if so, increment upper 40 bits */
1597 mtspr SPRN_TBU40,r8
1608 lis r8,0x7fff /* MAX_INT@h */
1609 mtspr SPRN_HDEC,r8
1611 16: ld r8,KVM_HOST_LPCR(r4)
1612 mtspr SPRN_LPCR,r8
1616 ld r8,PACA_SLBSHADOWPTR(r13)
1620 LDX_BE r5, r8, r3
1622 LDX_BE r6, r8, r3
1626 1: addi r8,r8,16
1694 lwz r8, VCPU_XER(r9)
1696 mtxer r8
1705 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */
1716 lwz r8, 0(r10)
1720 stw r8, VCPU_LAST_INST(r9)
2094 lwz r8,VCORE_ENTRY_EXIT(r5)
2095 clrldi r8,r8,56
2101 cmpw r4,r8
2415 li r8, XICS_MFRR
2416 stbcix r3, r6, r8 /* clear the IPI */
2441 stbcix r0, r6, r8 /* set the IPI */
2456 ori r8,r5,MSR_FP
2459 oris r8,r8,MSR_VEC@h
2464 oris r8,r8,MSR_VSX@h
2467 mtmsrd r8
2491 ori r8,r9,MSR_FP
2494 oris r8,r8,MSR_VEC@h
2499 oris r8,r8,MSR_VSX@h
2502 mtmsrd r8
2583 lbz r8, VCORE_IN_GUEST(r5)
2584 cmpwi r8, 0
2586 ld r8, VCORE_TB_OFFSET(r5) /* subtract timebase offset */
2591 subf r7, r8, r7
2596 ld r8, TAS_SEQCOUNT(r5)
2597 cmpdi r8, 0
2598 addi r8, r8, 1
2599 std r8, TAS_SEQCOUNT(r5)
2614 addi r8, r8, 1
2615 std r8, TAS_SEQCOUNT(r5)