Lines Matching refs:r5
82 addi r5,r7,-1
83 andc r6,r3,r5 /* round low to line bdy */
85 add r8,r8,r5 /* ensure we get enough */
98 addi r5,r7,-1
99 andc r6,r3,r5 /* round low to line bdy */
101 add r8,r8,r5
128 addi r5,r7,-1
129 andc r6,r3,r5 /* round low to line bdy */
131 add r8,r8,r5 /* ensure we get enough */
155 addi r5,r7,-1
156 andc r6,r3,r5 /* round low to line bdy */
158 add r8,r8,r5 /* ensure we get enough */
162 mfmsr r5 /* Disable MMU Data Relocation */
163 ori r0,r5,MSR_DR
175 mtmsr r5 /* Re-enable MMU Data Relocation */
183 addi r5,r7,-1
184 andc r6,r3,r5 /* round low to line bdy */
186 add r8,r8,r5 /* ensure we get enough */
224 lwz r5,DCACHEL1LINESIZE(r7) /* Get dcache line size */
228 add r6,r6,r5
235 lwz r5,ICACHEL1LINESIZE(r7) /* Get icache line size */
238 add r3,r3,r5
262 mfspr r5,SPRN_HID4
263 or r5,r5,r3
265 mtspr SPRN_HID4,r5
277 mfspr r5,SPRN_HID4
278 andc r5,r5,r3
280 mtspr SPRN_HID4,r5
302 rldicl r5,r6,32,0
303 ori r5,r5,0x100
304 rldicl r5,r5,32,0
306 mtspr SPRN_HID4,r5
333 rldicl r5,r6,32,0
334 ori r5,r5,0x100
335 rldicl r5,r5,32,0
337 mtspr SPRN_HID4,r5
435 mfmsr r5
436 ori r0,r5,MSR_EE
455 mtmsrd r5,1
471 1: mflr r5
472 addi r5,r5,kexec_flag-1b
476 lwz r4,0(r5)
566 mr r29,r5 /* image (virt) */
587 li r5,0x100
593 mflr r5
634 li r5,0