Lines Matching refs:r8
579 add r10, r10, r8 ;b 151f
721 lis r8, MI_RSV4I@h
722 ori r8, r8, 0x1c00
724 mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */
729 mr r8, r10
742 lis r8, KERNELBASE@h /* Create vaddr for TLB */
743 ori r8, r8, MI_EVALID /* Mark it valid */
744 mtspr SPRN_MI_EPN, r8
745 mtspr SPRN_MD_EPN, r8
746 li r8, MI_PS8MEG /* Set 8M byte page */
747 ori r8, r8, MI_SVALID /* Make it valid */
748 mtspr SPRN_MI_TWC, r8
749 mtspr SPRN_MD_TWC, r8
750 li r8, MI_BOOTINIT /* Create RPN for address 0 */
751 mtspr SPRN_MI_RPN, r8 /* Store TLB entry */
752 mtspr SPRN_MD_RPN, r8
753 lis r8, MI_Kp@h /* Set the protection mode */
754 mtspr SPRN_MI_AP, r8
755 mtspr SPRN_MD_AP, r8
767 mr r8, r9 /* Create vaddr for TLB */
768 ori r8, r8, MD_EVALID /* Mark it valid */
769 mtspr SPRN_MD_EPN, r8
770 li r8, MD_PS8MEG /* Set 8M byte page */
771 ori r8, r8, MD_SVALID /* Make it valid */
772 mtspr SPRN_MD_TWC, r8
773 mr r8, r9 /* Create paddr for TLB */
774 ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */
775 mtspr SPRN_MD_RPN, r8
783 lis r8, KERNELBASE@h /* Create vaddr for TLB */
784 addis r8, r8, 0x0080 /* Add 8M */
785 ori r8, r8, MI_EVALID /* Mark it valid */
786 mtspr SPRN_MD_EPN, r8
797 addis r8, r8, 0x0080 /* Add 8M */
798 mtspr SPRN_MD_EPN, r8
808 lis r8, IDC_INVALL@h
809 mtspr SPRN_IC_CST, r8
810 mtspr SPRN_DC_CST, r8
811 lis r8, IDC_ENABLE@h
812 mtspr SPRN_IC_CST, r8
814 mtspr SPRN_DC_CST, r8
819 lis r8, DC_SFWT@h
820 mtspr SPRN_DC_CST, r8
821 lis r8, IDC_ENABLE@h
822 mtspr SPRN_DC_CST, r8