Lines Matching refs:r11
124 mtspr SPRN_SPRG_SCRATCH1,r11; \
128 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \
129 andi. r11,r11,MSR_PR; \
130 tophys(r11,r1); /* use tophys(r1) if kernel */ \
132 mfspr r11,SPRN_SPRG_THREAD; \
133 lwz r11,THREAD_INFO-THREAD(r11); \
134 addi r11,r11,THREAD_SIZE; \
135 tophys(r11,r11); \
136 1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */
140 CLR_TOP32(r11); \
141 stw r10,_CCR(r11); /* save registers */ \
142 stw r12,GPR12(r11); \
143 stw r9,GPR9(r11); \
145 stw r10,GPR10(r11); \
147 stw r12,GPR11(r11); \
149 stw r10,_LINK(r11); \
152 stw r1,GPR1(r11); \
153 stw r1,0(r11); \
154 tovirt(r1,r11); /* set new kernel sp */ \
157 stw r0,GPR0(r11); \
158 SAVE_4GPRS(3, r11); \
159 SAVE_2GPRS(7, r11)
167 mfspr r11,SPRN_SPRG_SCRATCH1
189 stw r10,_TRAP(r11); \
224 stw r4,_DAR(r11)
228 stw r5,_DSISR(r11)
252 stw r4,_DAR(r11)
256 stw r5,_DSISR(r11)
308 addi r11, r10, PAGE_SIZE
309 tlbie r11
310 addi r11, r10, -PAGE_SIZE
311 tlbie r11
320 andis. r11, r10, 0x8000 /* Address >= 0x80000000 */
322 mfspr r11, SPRN_M_TW /* Get level 1 table */
325 lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha
329 rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
330 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */
333 MTSPR_CPU6(SPRN_MI_TWC, r11, r3) /* Set segment attributes */
334 rlwinm r11, r11,0,0,19 /* Extract page descriptor page address */
337 lwzx r10, r10, r11 /* Get the pte */
340 rlwinm r11, r10, 32-5, _PAGE_PRESENT
341 and r11, r11, r10
342 rlwimi r10, r11, 0, _PAGE_PRESENT
344 li r11, RPN_PATTERN
351 rlwimi r10, r11, 0, 0x07f8 /* Set 24-27, clear 21-23,28 */
357 mtspr SPRN_DAR, r11 /* Tag DAR */
375 andis. r11, r10, 0x8000
376 mfspr r11, SPRN_M_TW /* Get level 1 table */
378 lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha
381 rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
382 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */
388 rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */
397 rlwimi r11, r10, 0, 27, 27
401 rlwimi r11, r10, 32-5, 30, 30
402 MTSPR_CPU6(SPRN_MD_TWC, r11, r3)
414 rlwinm r11, r10, 32-5, _PAGE_PRESENT
415 and r11, r11, r10
416 rlwimi r10, r11, 0, _PAGE_PRESENT
424 li r11, RPN_PATTERN
425 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
432 mtspr SPRN_DAR, r11 /* Tag DAR */
460 mfspr r11, SPRN_DAR
461 cmpwi cr0, r11, RPN_PATTERN
467 stw r5,_DSISR(r11)
506 andis. r11, r10, 0x8000 /* Address >= 0x80000000 */
507 mfspr r11, SPRN_M_TW /* Get level 1 table */
509 lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha
511 3: rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
512 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */
513 rlwinm r11, r11,0,0,19 /* Extract page descriptor page address */
515 rlwimi r11, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
516 lwz r11, 0(r11) /* Get the pte */
518 rlwimi r11, r10, 0, 32 - PAGE_SHIFT, 31
519 lwz r11,0(r11)
523 xoris r10, r11, 0x7c00 /* check if major OP code is 31 */
543 andis. r10,r11,0x1f /* test if reg RA is r0 */
546 rlwinm r11,r11,0,0,20 /* Zero lower 10 bits */
547 oris r11,r11,640 /* Transform instr. to a "add r10,RA,RB" */
548 ori r11,r11,532
549 stw r11,0(r10) /* store add/and instruction */
552 mfspr r11, SPRN_SPRG_SCRATCH1 /* restore r11 */
565 rlwinm r10, r11, 24, 24, 28 /* offset into jump table for reg RB */
581 mtctr r11 ;b 154f /* r10 needs special handling */
582 mtctr r11 ;b 153f /* r11 needs special handling */
604 rlwinm. r11,r11,19,24,28 /* offset into jump table for reg RA */
606 addi r11, r11, 150b@l /* add start of table */
607 mtctr r11 /* load ctr with jump address */
608 rlwinm r11,r11,0,16,10 /* make sure we don't execute this more than once */
611 mfdar r11
612 mtctr r11 /* restore ctr reg from DAR */
618 153: mfspr r11, SPRN_SPRG_SCRATCH1 /* load r11 from SPRN_SPRG_SCRATCH1 */
619 add r10, r10, r11 /* add it */
620 mfctr r11 /* restore r11 */
622 154: mfspr r11, SPRN_SPRG_SCRATCH0 /* load r10 from SPRN_SPRG_SCRATCH0 */
623 add r10, r10, r11 /* add it */
624 mfctr r11 /* restore r11 */
790 li r11, MI_BOOTINIT /* Create RPN for address 0 */
791 addis r11, r11, 0x0080 /* Add 8M */
792 mtspr SPRN_MD_RPN, r11
800 addis r11, r11, 0x0080 /* Add 8M */
801 mtspr SPRN_MD_RPN, r11