Lines Matching refs:r10
123 mtspr SPRN_SPRG_SCRATCH0,r10; \
125 mfcr r10
141 stw r10,_CCR(r11); /* save registers */ \
144 mfspr r10,SPRN_SPRG_SCRATCH0; \
145 stw r10,GPR10(r11); \
148 mflr r10; \
149 stw r10,_LINK(r11); \
155 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
156 MTMSRD(r10); /* (except for mach check in rtas) */ \
165 mtcr r10; \
166 mfspr r10,SPRN_SPRG_SCRATCH0; \
188 li r10,trap; \
189 stw r10,_TRAP(r11); \
190 li r10,MSR_KERNEL; \
191 copyee(r10, r9); \
305 mtspr SPRN_SPRG_SCRATCH2, r10
306 mfspr r10, SPRN_SRR0 /* Get effective address of fault */
308 addi r11, r10, PAGE_SIZE
310 addi r11, r10, -PAGE_SIZE
320 andis. r11, r10, 0x8000 /* Address >= 0x80000000 */
329 rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
336 rlwinm r10, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
337 lwzx r10, r10, r11 /* Get the pte */
340 rlwinm r11, r10, 32-5, _PAGE_PRESENT
341 and r11, r11, r10
342 rlwimi r10, r11, 0, _PAGE_PRESENT
351 rlwimi r10, r11, 0, 0x07f8 /* Set 24-27, clear 21-23,28 */
352 MTSPR_CPU6(SPRN_MI_RPN, r10, r3) /* Update TLB entry */
359 mfspr r10, SPRN_SPRG_SCRATCH2
369 mtspr SPRN_SPRG_SCRATCH2, r10
370 mfspr r10, SPRN_MD_EPN
375 andis. r11, r10, 0x8000
381 rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
387 rlwinm r10, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
388 rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */
389 lwz r10, 0(r10) /* Get the pte */
397 rlwimi r11, r10, 0, 27, 27
401 rlwimi r11, r10, 32-5, 30, 30
414 rlwinm r11, r10, 32-5, _PAGE_PRESENT
415 and r11, r11, r10
416 rlwimi r10, r11, 0, _PAGE_PRESENT
425 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
426 MTSPR_CPU6(SPRN_MD_RPN, r10, r3) /* Update TLB entry */
433 mfspr r10, SPRN_SPRG_SCRATCH2
446 andis. r10,r5,0x4000
469 andis. r10,r5,0x4000
472 1: li r10,RPN_PATTERN
473 mtspr SPRN_DAR,r10 /* Tag DAR, to be used in DTLB Error */
503 mtspr SPRN_SPRG_SCRATCH2, r10
505 mfspr r10, SPRN_SRR0
506 andis. r11, r10, 0x8000 /* Address >= 0x80000000 */
511 3: rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
515 rlwimi r11, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
518 rlwimi r11, r10, 0, 32 - PAGE_SHIFT, 31
523 xoris r10, r11, 0x7c00 /* check if major OP code is 31 */
524 rlwinm r10, r10, 0, 21, 5
525 cmpwi cr0, r10, 2028 /* Is dcbz? */
527 cmpwi cr0, r10, 940 /* Is dcbi? */
529 cmpwi cr0, r10, 108 /* Is dcbst? */
531 cmpwi cr0, r10, 172 /* Is dcbf? */
533 cmpwi cr0, r10, 1964 /* Is icbi? */
535 141: mfspr r10,SPRN_SPRG_SCRATCH2
538 144: mfspr r10, SPRN_DSISR
539 rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */
540 mtspr SPRN_DSISR, r10
543 andis. r10,r11,0x1f /* test if reg RA is r0 */
544 li r10,modified_instr@l
545 dcbtst r0,r10 /* touch for store */
549 stw r11,0(r10) /* store add/and instruction */
550 dcbf 0,r10 /* flush new instr. to memory. */
551 icbi 0,r10 /* invalidate instr. cache line */
553 mfspr r10, SPRN_SPRG_SCRATCH0 /* restore r10 */
558 subf r10,r0,r10 /* r10=r10-r0, only if reg RA is r0 */
559 143: mtdar r10 /* store faulting EA in DAR */
560 mfspr r10,SPRN_SPRG_SCRATCH2
563 mfctr r10
564 mtdar r10 /* save ctr reg in DAR */
565 rlwinm r10, r11, 24, 24, 28 /* offset into jump table for reg RB */
566 addi r10, r10, 150f@l /* add start of table */
567 mtctr r10 /* load ctr with jump address */
568 xor r10, r10, r10 /* sum starts at zero */
571 add r10, r10, r0 ;b 151f
572 add r10, r10, r1 ;b 151f
573 add r10, r10, r2 ;b 151f
574 add r10, r10, r3 ;b 151f
575 add r10, r10, r4 ;b 151f
576 add r10, r10, r5 ;b 151f
577 add r10, r10, r6 ;b 151f
578 add r10, r10, r7 ;b 151f
579 add r10, r10, r8 ;b 151f
580 add r10, r10, r9 ;b 151f
583 add r10, r10, r12 ;b 151f
584 add r10, r10, r13 ;b 151f
585 add r10, r10, r14 ;b 151f
586 add r10, r10, r15 ;b 151f
587 add r10, r10, r16 ;b 151f
588 add r10, r10, r17 ;b 151f
589 add r10, r10, r18 ;b 151f
590 add r10, r10, r19 ;b 151f
591 add r10, r10, r20 ;b 151f
592 add r10, r10, r21 ;b 151f
593 add r10, r10, r22 ;b 151f
594 add r10, r10, r23 ;b 151f
595 add r10, r10, r24 ;b 151f
596 add r10, r10, r25 ;b 151f
597 add r10, r10, r26 ;b 151f
598 add r10, r10, r27 ;b 151f
599 add r10, r10, r28 ;b 151f
600 add r10, r10, r29 ;b 151f
601 add r10, r10, r30 ;b 151f
602 add r10, r10, r31
613 mtdar r10 /* save fault EA to DAR */
614 mfspr r10,SPRN_SPRG_SCRATCH2
619 add r10, r10, r11 /* add it */
623 add r10, r10, r11 /* add it */
727 lis r10, (MD_RSV4I | MD_RESETVAL)@h
728 ori r10, r10, 0x1c00
729 mr r8, r10
731 lis r10, MD_RESETVAL@h
734 oris r10, r10, MD_WTDEF@h
736 mtspr SPRN_MD_CTR, r10 /* Set data TLB control */
761 addi r10, r10, 0x0100
762 mtspr SPRN_MD_CTR, r10
780 addi r10, r10, 0x0100
781 mtspr SPRN_MD_CTR, r10
794 addi r10, r10, 0x0100
795 mtspr SPRN_MD_CTR, r10