Lines Matching refs:li
65 li r24,0 /* CPU number */
113 li r0,0
158 li r4, 0 /* higer 32bit */
204 li r3,0
220 li r0,0
357 li r13,_PAGE_PRESENT|_PAGE_ACCESSED
389 li r13,0
455 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
485 li r13,0
527 li r11,PPC44x_TLB_VALID | PPC44x_TLBE_SIZE
533 li r10,0xf85 /* Mask to apply from PTE */
571 li r12,0 /* MMUCR = 0 */
594 li r13,_PAGE_PRESENT|_PAGE_ACCESSED
603 li r12,PPC47x_TLB0_VALID | PPC47x_TLBE_SIZE
605 li r12,0
668 li r12,0 /* MMUCR = 0 */
678 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
686 li r12,PPC47x_TLB0_VALID | PPC47x_TLBE_SIZE
688 li r12,0
744 li r10,0xf85 /* Mask to apply from PTE */
782 li r3,MachineCheckA@l
869 li r4,0 /* Start at TLB entry 0 */
870 li r3,0 /* Set PAGEID inval value */
903 li r4, 0 /* Load the kernel physical address */
907 li r0,0
912 li r5,0
926 li r5,0
929 li r0,63 /* TLB slot 63 */
947 li r6,0
964 li r5,(PPC44x_TLB_SW|PPC44x_TLB_SR|PPC44x_TLB_I|PPC44x_TLB_G)
965 li r0,62 /* TLB slot 0 */
1016 li r0,0
1029 li r0,0
1070 li r5,0
1115 li r0,0
1126 li r5,0
1178 li r5,(PPC47x_TLB2_S_RW | PPC47x_TLB2_IMG)