Lines Matching refs:eeh_ops
693 eeh_ops->read_config(pdn, cap + PCI_EXP_SLTSTA, 2, &val); in eeh_bridge_check_link()
700 eeh_ops->read_config(pdn, cap + PCI_EXP_SLTCAP, 2, &val); in eeh_bridge_check_link()
702 eeh_ops->read_config(pdn, cap + PCI_EXP_SLTCTL, 2, &val); in eeh_bridge_check_link()
707 eeh_ops->write_config(pdn, cap + PCI_EXP_SLTCTL, 2, val); in eeh_bridge_check_link()
713 eeh_ops->read_config(pdn, cap + PCI_EXP_LNKCTL, 2, &val); in eeh_bridge_check_link()
715 eeh_ops->write_config(pdn, cap + PCI_EXP_LNKCTL, 2, val); in eeh_bridge_check_link()
718 eeh_ops->read_config(pdn, cap + PCI_EXP_LNKCAP, 4, &val); in eeh_bridge_check_link()
731 eeh_ops->read_config(pdn, cap + PCI_EXP_LNKSTA, 2, &val); in eeh_bridge_check_link()
756 eeh_ops->write_config(pdn, i*4, 4, edev->config_space[i]); in eeh_restore_bridge_bars()
758 eeh_ops->write_config(pdn, 14*4, 4, edev->config_space[14]); in eeh_restore_bridge_bars()
761 eeh_ops->write_config(pdn, PCI_CACHE_LINE_SIZE, 1, in eeh_restore_bridge_bars()
763 eeh_ops->write_config(pdn, PCI_LATENCY_TIMER, 1, in eeh_restore_bridge_bars()
766 eeh_ops->write_config(pdn, 15*4, 4, edev->config_space[15]); in eeh_restore_bridge_bars()
769 eeh_ops->write_config(pdn, PCI_COMMAND, 4, edev->config_space[1]); in eeh_restore_bridge_bars()
782 eeh_ops->write_config(pdn, i*4, 4, edev->config_space[i]); in eeh_restore_device_bars()
784 eeh_ops->write_config(pdn, 12*4, 4, edev->config_space[12]); in eeh_restore_device_bars()
786 eeh_ops->write_config(pdn, PCI_CACHE_LINE_SIZE, 1, in eeh_restore_device_bars()
788 eeh_ops->write_config(pdn, PCI_LATENCY_TIMER, 1, in eeh_restore_device_bars()
792 eeh_ops->write_config(pdn, 15*4, 4, edev->config_space[15]); in eeh_restore_device_bars()
798 eeh_ops->read_config(pdn, PCI_COMMAND, 4, &cmd); in eeh_restore_device_bars()
807 eeh_ops->write_config(pdn, PCI_COMMAND, 4, cmd); in eeh_restore_device_bars()
830 if (eeh_ops->restore_config && pdn) in eeh_restore_one_device_bars()
831 eeh_ops->restore_config(pdn); in eeh_restore_one_device_bars()