115 struct eeh_ops *eeh_ops = NULL;  variable
180 	eeh_ops->read_config(pdn, PCI_VENDOR_ID, 4, &cfg);  in eeh_dump_dev_log()
184 	eeh_ops->read_config(pdn, PCI_COMMAND, 4, &cfg);  in eeh_dump_dev_log()
190 		eeh_ops->read_config(pdn, PCI_SEC_STATUS, 2, &cfg);  in eeh_dump_dev_log()
194 		eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &cfg);  in eeh_dump_dev_log()
202 		eeh_ops->read_config(pdn, cap, 4, &cfg);  in eeh_dump_dev_log()
206 		eeh_ops->read_config(pdn, cap+4, 4, &cfg);  in eeh_dump_dev_log()
218 			eeh_ops->read_config(pdn, cap+4*i, 4, &cfg);  in eeh_dump_dev_log()
245 			eeh_ops->read_config(pdn, cap+4*i, 4, &cfg);  in eeh_dump_dev_log()
326 		eeh_ops->configure_bridge(pe);  in eeh_slot_error_detail()
335 	eeh_ops->get_log(pe, severity, pci_regs_buf, loglen);  in eeh_slot_error_detail()
395 	ret = eeh_ops->get_state(phb_pe, NULL);  in eeh_phb_check_failure()
518 	ret = eeh_ops->get_state(pe, NULL);  in eeh_dev_check_failure()
547 		ret = eeh_ops->get_state(parent_pe, NULL);  in eeh_dev_check_failure()
656 		rc = eeh_ops->get_state(pe, NULL);  in eeh_pci_enable()
671 	rc = eeh_ops->set_option(pe, function);  in eeh_pci_enable()
680 		rc = eeh_ops->wait_state(pe, PCI_BUS_RESET_WAIT_MSEC);  in eeh_pci_enable()
732 	if (pdn && eeh_ops->restore_config)  in eeh_restore_dev_state()
733 		eeh_ops->restore_config(pdn);  in eeh_restore_dev_state()
763 		eeh_ops->reset(pe, EEH_RESET_DEACTIVATE);  in pcibios_set_pcie_reset_state()
771 		eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);  in pcibios_set_pcie_reset_state()
774 		eeh_ops->reset(pe, EEH_RESET_HOT);  in pcibios_set_pcie_reset_state()
778 		eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);  in pcibios_set_pcie_reset_state()
781 		eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL);  in pcibios_set_pcie_reset_state()
833 		eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL);  in eeh_reset_pe_once()
835 		eeh_ops->reset(pe, EEH_RESET_HOT);  in eeh_reset_pe_once()
837 	eeh_ops->reset(pe, EEH_RESET_DEACTIVATE);  in eeh_reset_pe_once()
864 		state = eeh_ops->wait_state(pe, PCI_BUS_RESET_WAIT_MSEC);  in eeh_reset_pe()
907 		eeh_ops->read_config(pdn, i * 4, 4, &edev->config_space[i]);  in eeh_save_bars()
927 int __init eeh_ops_register(struct eeh_ops *ops)  in eeh_ops_register()
935 	if (eeh_ops && eeh_ops != ops) {  in eeh_ops_register()
937 			__func__, eeh_ops->name, ops->name);  in eeh_ops_register()
941 	eeh_ops = ops;  in eeh_ops_register()
961 	if (eeh_ops && !strcmp(eeh_ops->name, name)) {  in eeh_ops_unregister()
962 		eeh_ops = NULL;  in eeh_ops_unregister()
1020 	if (!eeh_ops) {  in eeh_init()
1024 	} else if ((ret = eeh_ops->init()))  in eeh_init()
1035 		traverse_pci_dn(pdn, eeh_ops->probe, NULL);  in eeh_init()
1043 	if (eeh_ops->post_init) {  in eeh_init()
1044 		ret = eeh_ops->post_init();  in eeh_init()
1088 	eeh_ops->probe(pdn, NULL);  in eeh_add_device_early()
1160 		eeh_ops->probe(pdn, NULL);  in eeh_add_device_late()
1308 	ret = eeh_ops->get_state(pe, NULL);  in eeh_pe_change_owner()
1508 		if (!eeh_ops || !eeh_ops->set_option) {  in eeh_pe_set_option()
1541 	if (!eeh_ops || !eeh_ops->get_state)  in eeh_pe_get_state()
1544 	result = eeh_ops->get_state(pe, NULL);  in eeh_pe_get_state()
1611 	if (!eeh_ops || !eeh_ops->set_option || !eeh_ops->reset)  in eeh_pe_reset()
1616 		ret = eeh_ops->reset(pe, option);  in eeh_pe_reset()
1630 		eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);  in eeh_pe_reset()
1633 		ret = eeh_ops->reset(pe, option);  in eeh_pe_reset()
1713 	if (eeh_ops->post_init)  in eeh_enable_dbgfs_set()
1714 		eeh_ops->post_init();  in eeh_enable_dbgfs_set()