Lines Matching refs:__MASK
62 #define __MASK(X) (1<<(X)) macro
64 #define __MASK(X) (1UL<<(X)) macro
68 #define MSR_SF __MASK(MSR_SF_LG) /* Enable 64 bit mode */
69 #define MSR_ISF __MASK(MSR_ISF_LG) /* Interrupt 64b mode valid on 630 */
70 #define MSR_HV __MASK(MSR_HV_LG) /* Hypervisor state */
78 #define MSR_VEC __MASK(MSR_VEC_LG) /* Enable AltiVec */
79 #define MSR_VSX __MASK(MSR_VSX_LG) /* Enable VSX */
80 #define MSR_POW __MASK(MSR_POW_LG) /* Enable Power Management */
81 #define MSR_WE __MASK(MSR_WE_LG) /* Wait State Enable */
82 #define MSR_TGPR __MASK(MSR_TGPR_LG) /* TLB Update registers in use */
83 #define MSR_CE __MASK(MSR_CE_LG) /* Critical Interrupt Enable */
84 #define MSR_ILE __MASK(MSR_ILE_LG) /* Interrupt Little Endian */
85 #define MSR_EE __MASK(MSR_EE_LG) /* External Interrupt Enable */
86 #define MSR_PR __MASK(MSR_PR_LG) /* Problem State / Privilege Level */
87 #define MSR_FP __MASK(MSR_FP_LG) /* Floating Point enable */
88 #define MSR_ME __MASK(MSR_ME_LG) /* Machine Check Enable */
89 #define MSR_FE0 __MASK(MSR_FE0_LG) /* Floating Exception mode 0 */
90 #define MSR_SE __MASK(MSR_SE_LG) /* Single Step */
91 #define MSR_BE __MASK(MSR_BE_LG) /* Branch Trace */
92 #define MSR_DE __MASK(MSR_DE_LG) /* Debug Exception Enable */
93 #define MSR_FE1 __MASK(MSR_FE1_LG) /* Floating Exception mode 1 */
94 #define MSR_IP __MASK(MSR_IP_LG) /* Exception prefix 0x000/0xFFF */
95 #define MSR_IR __MASK(MSR_IR_LG) /* Instruction Relocate */
96 #define MSR_DR __MASK(MSR_DR_LG) /* Data Relocate */
97 #define MSR_PE __MASK(MSR_PE_LG) /* Protection Enable */
98 #define MSR_PX __MASK(MSR_PX_LG) /* Protection Exclusive Mode */
100 #define MSR_PMM __MASK(MSR_PMM_LG) /* Performance monitor */
102 #define MSR_RI __MASK(MSR_RI_LG) /* Recoverable Exception */
103 #define MSR_LE __MASK(MSR_LE_LG) /* Little Endian */
105 #define MSR_TM __MASK(MSR_TM_LG) /* Transactional Mem Available */
107 #define MSR_TS_S __MASK(MSR_TS_S_LG) /* Transaction Suspended */
108 #define MSR_TS_T __MASK(MSR_TS_T_LG) /* Transaction Transactional */
220 #define TEXASR_FS __MASK(63-36) /* TEXASR Failure Summary */
238 #define DAWRX_USER __MASK(0)
239 #define DAWRX_KERNEL __MASK(1)
240 #define DAWRX_HYP __MASK(2)
241 #define DAWRX_WTI __MASK(3)
242 #define DAWRX_WT __MASK(4)
243 #define DAWRX_DR __MASK(5)
244 #define DAWRX_DW __MASK(6)
248 #define DABRX_USER __MASK(0)
249 #define DABRX_KERNEL __MASK(1)
250 #define DABRX_HYP __MASK(2)
251 #define DABRX_BTI __MASK(3)
296 #define FSCR_TAR __MASK(FSCR_TAR_LG)
297 #define FSCR_EBB __MASK(FSCR_EBB_LG)
298 #define FSCR_DSCR __MASK(FSCR_DSCR_LG)
300 #define HFSCR_TAR __MASK(FSCR_TAR_LG)
301 #define HFSCR_EBB __MASK(FSCR_EBB_LG)
302 #define HFSCR_TM __MASK(FSCR_TM_LG)
303 #define HFSCR_PM __MASK(FSCR_PM_LG)
304 #define HFSCR_BHRB __MASK(FSCR_BHRB_LG)
305 #define HFSCR_DSCR __MASK(FSCR_DSCR_LG)
306 #define HFSCR_VECVSX __MASK(FSCR_VECVSX_LG)
307 #define HFSCR_FP __MASK(FSCR_FP_LG)
445 #define HID0_POWER8_4LPARMODE __MASK(61)
446 #define HID0_POWER8_2LPARMODE __MASK(57)
447 #define HID0_POWER8_1TO2LPAR __MASK(52)
448 #define HID0_POWER8_1TO4LPAR __MASK(51)
449 #define HID0_POWER8_DYNLPARDIS __MASK(48)