Lines Matching refs:__be32
27 __be32 iadd; /* I-RAM Address Register */
28 __be32 idata; /* I-RAM Data Register */
30 __be32 iready; /* I-RAM Ready Register */
36 __be32 qicr;
37 __be32 qivec;
38 __be32 qripnr;
39 __be32 qipnr;
40 __be32 qipxcc;
41 __be32 qipycc;
42 __be32 qipwcc;
43 __be32 qipzcc;
44 __be32 qimr;
45 __be32 qrimr;
46 __be32 qicnr;
48 __be32 qiprta;
49 __be32 qiprtb;
51 __be32 qricr;
53 __be32 qhivec;
59 __be32 cecr; /* QE command register */
60 __be32 ceccr; /* QE controller configuration register */
61 __be32 cecdr; /* QE command data register */
66 __be32 cetscr; /* QE time-stamp timer control register */
67 __be32 cetsr1; /* QE time-stamp register 1 */
68 __be32 cetsr2; /* QE time-stamp register 2 */
70 __be32 cevter; /* QE virtual tasks event register */
71 __be32 cevtmr; /* QE virtual tasks mask register */
91 __be32 ceurnr; /* QE microcode revision number register */
97 __be32 cmxgcr; /* CMX general clock route register */
98 __be32 cmxsi1cr_l; /* CMX SI1 clock route low register */
99 __be32 cmxsi1cr_h; /* CMX SI1 clock route high register */
100 __be32 cmxsi1syr; /* CMX SI1 SYNC route register */
101 __be32 cmxucr[4]; /* CMX UCCx clock route registers */
102 __be32 cmxupcr; /* CMX UPC clock route register */
138 __be32 brgc[16]; /* BRG configuration registers */
145 __be32 spmode; /* SPI mode register */
155 __be32 spitd; /* SPI transmit data register (cpu mode) */
156 __be32 spird; /* SPI receive data register (cpu mode) */
202 __be32 siml1; /* SI1 multiframe limit register */
235 __be32 mcce; /* MCC event register */
236 __be32 mccm; /* MCC mask register */
237 __be32 mccf; /* MCC configuration register */
238 __be32 merl; /* MCC emergency request level register */
244 __be32 gumr_l; /* UCCx general mode register (low) */
245 __be32 gumr_h; /* UCCx general mode register (high) */
263 __be32 gumr; /* UCCx general mode register */
264 __be32 upsmr; /* UCCx protocol-specific mode register */
269 __be32 ucce; /* UCCx event register */
270 __be32 uccm; /* UCCx mask register */
273 __be32 urfb; /* UCC receive FIFO base */
279 __be32 utfb; /* UCC transmit FIFO base */
288 __be32 urtry; /* UCC retry counter register */
303 __be32 upgcr; /* UTOPIA/POS general configuration register */
304 __be32 uplpa; /* UTOPIA/POS last PHY address */
305 __be32 uphec; /* ATM HEC register */
306 __be32 upuc; /* UTOPIA/POS UCC configuration */
307 __be32 updc1; /* UTOPIA/POS device 1 configuration */
308 __be32 updc2; /* UTOPIA/POS device 2 configuration */
309 __be32 updc3; /* UTOPIA/POS device 3 configuration */
310 __be32 updc4; /* UTOPIA/POS device 4 configuration */
311 __be32 upstpa; /* UTOPIA/POS STPA threshold */
313 __be32 updrs1_h; /* UTOPIA/POS device 1 rate select */
314 __be32 updrs1_l; /* UTOPIA/POS device 1 rate select */
315 __be32 updrs2_h; /* UTOPIA/POS device 2 rate select */
316 __be32 updrs2_l; /* UTOPIA/POS device 2 rate select */
317 __be32 updrs3_h; /* UTOPIA/POS device 3 rate select */
318 __be32 updrs3_l; /* UTOPIA/POS device 3 rate select */
319 __be32 updrs4_h; /* UTOPIA/POS device 4 rate select */
320 __be32 updrs4_l; /* UTOPIA/POS device 4 rate select */
321 __be32 updrp1; /* UTOPIA/POS device 1 receive priority low */
322 __be32 updrp2; /* UTOPIA/POS device 2 receive priority low */
323 __be32 updrp3; /* UTOPIA/POS device 3 receive priority low */
324 __be32 updrp4; /* UTOPIA/POS device 4 receive priority low */
325 __be32 upde1; /* UTOPIA/POS device 1 event */
326 __be32 upde2; /* UTOPIA/POS device 2 event */
327 __be32 upde3; /* UTOPIA/POS device 3 event */
328 __be32 upde4; /* UTOPIA/POS device 4 event */
350 __be32 uper1; /* Device 1 port enable register */
351 __be32 uper2; /* Device 2 port enable register */
352 __be32 uper3; /* Device 3 port enable register */
353 __be32 uper4; /* Device 4 port enable register */
359 __be32 sdsr; /* Serial DMA status register */
360 __be32 sdmr; /* Serial DMA mode register */
361 __be32 sdtr1; /* SDMA system bus threshold register */
362 __be32 sdtr2; /* SDMA secondary bus threshold register */
363 __be32 sdhy1; /* SDMA system bus hysteresis register */
364 __be32 sdhy2; /* SDMA secondary bus hysteresis register */
365 __be32 sdta1; /* SDMA system bus address register */
366 __be32 sdta2; /* SDMA secondary bus address register */
367 __be32 sdtm1; /* SDMA system bus MSNUM register */
368 __be32 sdtm2; /* SDMA secondary bus MSNUM register */
370 __be32 sdaqr; /* SDMA address bus qualify register */
371 __be32 sdaqmr; /* SDMA address bus qualify mask register */
373 __be32 sdebcr; /* SDMA CAM entries base register */
379 __be32 bpdcr; /* Breakpoint debug command register */
380 __be32 bpdsr; /* Breakpoint debug status register */
381 __be32 bpdmr; /* Breakpoint debug mask register */
382 __be32 bprmrr0; /* Breakpoint request mode risc register 0 */
383 __be32 bprmrr1; /* Breakpoint request mode risc register 1 */
385 __be32 bprmtr0; /* Breakpoint request mode trb register 0 */
386 __be32 bprmtr1; /* Breakpoint request mode trb register 1 */
388 __be32 bprmir; /* Breakpoint request mode immediate register */
389 __be32 bprmsr; /* Breakpoint request mode serial register */
390 __be32 bpemr; /* Breakpoint exit mode register */
399 __be32 tibcr[16]; /* Trap/instruction breakpoint control regs */
401 __be32 ibcr0;
402 __be32 ibs0;
403 __be32 ibcnr0;
405 __be32 ibcr1;
406 __be32 ibs1;
407 __be32 ibcnr1;
408 __be32 npcr;
409 __be32 dbcr;
410 __be32 dbar;
411 __be32 dbamr;
412 __be32 dbsr;
413 __be32 dbcnr;
415 __be32 dbdr_h;
416 __be32 dbdr_l;
417 __be32 dbdmr_h;
418 __be32 dbdmr_l;
419 __be32 bsr;
420 __be32 bor;
421 __be32 bior;
423 __be32 iatr[4];
424 __be32 eccr; /* Exception control configuration register */
425 __be32 eicr;