Lines Matching defs:fsl_lbc_regs
103 struct fsl_lbc_regs { struct
104 struct fsl_lbc_bank bank[12];
105 u8 res0[0x8];
106 __be32 mar; /**< UPM Address Register */
107 u8 res1[0x4];
108 __be32 mamr; /**< UPMA Mode Register */
114 __be32 mbmr; /**< UPMB Mode Register */
115 __be32 mcmr; /**< UPMC Mode Register */
116 u8 res2[0x8];
117 __be32 mrtpr; /**< Memory Refresh Timer Prescaler Register */
118 __be32 mdr; /**< UPM Data Register */
119 u8 res3[0x4];
120 __be32 lsor; /**< Special Operation Initiation Register */
121 __be32 lsdmr; /**< SDRAM Mode Register */
122 u8 res4[0x8];
123 __be32 lurt; /**< UPM Refresh Timer */
124 __be32 lsrt; /**< SDRAM Refresh Timer */
125 u8 res5[0x8];
126 __be32 ltesr; /**< Transfer Error Status Register */
145 __be32 ltedr; /**< Transfer Error Disable Register */
146 __be32 lteir; /**< Transfer Error Interrupt Register */
147 __be32 lteatr; /**< Transfer Error Attributes Register */
148 __be32 ltear; /**< Transfer Error Address Register */
149 __be32 lteccr; /**< Transfer Error ECC Register */
150 u8 res6[0x8];
151 __be32 lbcr; /**< Configuration Register */
166 __be32 lcrr; /**< Clock Ratio Register */
177 u8 res7[0x8];
178 __be32 fmr; /**< Flash Mode Register */
187 __be32 fir; /**< Flash Instruction Register */
220 __be32 fcr; /**< Flash Command Register */
229 __be32 fbar; /**< Flash Block Address Register */
231 __be32 fpar; /**< Flash Page Address Register */
242 __be32 fbcr; /**< Flash Byte Count Register */