Lines Matching defs:ccsr_guts
30 struct ccsr_guts { struct
31 __be32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
32 __be32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */
33 __be32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */
34 __be32 pordevsr; /* 0x.000c - POR I/O Device Status Register */
35 __be32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */
36 __be32 pordevsr2; /* 0x.0014 - POR device status register 2 */
37 u8 res018[0x20 - 0x18];
38 __be32 porcir; /* 0x.0020 - POR Configuration Information Register */
39 u8 res024[0x30 - 0x24];
40 __be32 gpiocr; /* 0x.0030 - GPIO Control Register */
41 u8 res034[0x40 - 0x34];
42 __be32 gpoutdr; /* 0x.0040 - General-Purpose Output Data Register */
43 u8 res044[0x50 - 0x44];
44 __be32 gpindr; /* 0x.0050 - General-Purpose Input Data Register */
45 u8 res054[0x60 - 0x54];
46 __be32 pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */
47 __be32 pmuxcr2; /* 0x.0064 - Alternate function signal multiplex control 2 */
48 __be32 dmuxcr; /* 0x.0068 - DMA Mux Control Register */
49 u8 res06c[0x70 - 0x6c];
50 __be32 devdisr; /* 0x.0070 - Device Disable Control */
53 __be32 devdisr2; /* 0x.0074 - Device Disable Control 2 */
54 u8 res078[0x7c - 0x78];
55 __be32 pmjcr; /* 0x.007c - 4 Power Management Jog Control Register */
56 __be32 powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */
57 __be32 pmrccr; /* 0x.0084 - Power Management Reset Counter Configuration Register */
58 __be32 pmpdccr; /* 0x.0088 - Power Management Power Down Counter Configuration Register */
59 __be32 pmcdr; /* 0x.008c - 4Power management clock disable register */
60 __be32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */
61 __be32 rstrscr; /* 0x.0094 - Reset Request Status and Control Register */
62 __be32 ectrstcr; /* 0x.0098 - Exception reset control register */
63 __be32 autorstsr; /* 0x.009c - Automatic reset status register */
64 __be32 pvr; /* 0x.00a0 - Processor Version Register */
65 __be32 svr; /* 0x.00a4 - System Version Register */
66 u8 res0a8[0xb0 - 0xa8];
67 __be32 rstcr; /* 0x.00b0 - Reset Control Register */
68 u8 res0b4[0xc0 - 0xb4];
69 __be32 iovselsr; /* 0x.00c0 - I/O voltage select status register
71 u8 res0c4[0x100 - 0xc4];
72 __be32 rcwsr[16]; /* 0x.0100 - Reset Control Word Status registers
74 u8 res140[0x224 - 0x140];
75 __be32 iodelay1; /* 0x.0224 - IO delay control register 1 */
76 __be32 iodelay2; /* 0x.0228 - IO delay control register 2 */
77 u8 res22c[0x604 - 0x22c];
78 __be32 pamubypenr; /* 0x.604 - PAMU bypass enable register */
79 u8 res608[0x800 - 0x608];
80 __be32 clkdvdr; /* 0x.0800 - Clock Divide Register */
81 u8 res804[0x900 - 0x804];
82 __be32 ircr; /* 0x.0900 - Infrared Control Register */
83 u8 res904[0x908 - 0x904];
84 __be32 dmacr; /* 0x.0908 - DMA Control Register */
85 u8 res90c[0x914 - 0x90c];
86 __be32 elbccr; /* 0x.0914 - eLBC Control Register */
87 u8 res918[0xb20 - 0x918];
88 __be32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */
89 __be32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */
90 __be32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */
91 u8 resb2c[0xe00 - 0xb2c];
92 __be32 clkocr; /* 0x.0e00 - Clock Out Select Register */
93 u8 rese04[0xe10 - 0xe04];
94 __be32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */
95 u8 rese14[0xe20 - 0xe14];
96 __be32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */
97 __be32 cpfor; /* 0x.0e24 - L2 charge pump fuse override register */
98 u8 rese28[0xf04 - 0xe28];
99 __be32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */
100 __be32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */
101 u8 resf0c[0xf2c - 0xf0c];
102 __be32 itcr; /* 0x.0f2c - Internal transaction control register */
103 u8 resf30[0xf40 - 0xf30];
104 __be32 srds2cr0; /* 0x.0f40 - SerDes2 Control Register 0 */
105 __be32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */