Lines Matching refs:u8
48 u32 mv64x60_cfg_read(u8 *bridge_base, u8 hose, u8 bus, u8 devfn,
49 u8 offset);
50 void mv64x60_cfg_write(u8 *bridge_base, u8 hose, u8 bus, u8 devfn,
51 u8 offset, u32 val);
53 void mv64x60_config_ctlr_windows(u8 *bridge_base, u8 *bridge_pbase,
54 u8 is_coherent);
55 void mv64x60_config_pci_windows(u8 *bridge_base, u8 *bridge_pbase, u8 hose,
56 u8 bus, u32 mem_size, u32 acc_bits);
57 void mv64x60_config_cpu2pci_window(u8 *bridge_base, u8 hose, u32 pci_base_hi,
60 u32 mv64x60_get_mem_size(u8 *bridge_base);
61 u8 *mv64x60_get_bridge_pbase(void);
62 u8 *mv64x60_get_bridge_base(void);
63 u8 mv64x60_is_coherent(void);
66 int mv64x60_i2c_read(u32 devaddr, u8 *buf, u32 offset, u32 offset_size,