181 u32 mv64x60_cfg_read(u8 *bridge_base, u8 hose, u8 bus, u8 devfn, u8 offset)  in mv64x60_cfg_read()  argument
183 	out_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].addr),  in mv64x60_cfg_read()
185 	return in_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].data));  in mv64x60_cfg_read()
188 void mv64x60_cfg_write(u8 *bridge_base, u8 hose, u8 bus, u8 devfn, u8 offset,  in mv64x60_cfg_write()  argument
191 	out_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].addr),  in mv64x60_cfg_write()
193 	out_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].data), val);  in mv64x60_cfg_write()
411 void mv64x60_config_pci_windows(u8 *bridge_base, u8 *bridge_pbase, u8 hose,  in mv64x60_config_pci_windows()  argument
418 	bar_enable = hose ? MV64x60_PCI1_BAR_ENABLE : MV64x60_PCI0_BAR_ENABLE;  in mv64x60_config_pci_windows()
422 		out_le32((u32 *)(bridge_base + mv64x60_pci_acc[hose][i].lo), 0);  in mv64x60_config_pci_windows()
429 	offset = hose ?  in mv64x60_config_pci_windows()
437 	mv64x60_cfg_write(bridge_base, hose, bus,  in mv64x60_config_pci_windows()
438 			PCI_DEVFN(0, mv64x60_pci2mem[hose].fcn),  in mv64x60_config_pci_windows()
439 			mv64x60_pci2mem[hose].hi, 0);  in mv64x60_config_pci_windows()
440 	mv64x60_cfg_write(bridge_base, hose, bus,  in mv64x60_config_pci_windows()
441 			PCI_DEVFN(0, mv64x60_pci2mem[hose].fcn),  in mv64x60_config_pci_windows()
442 			mv64x60_pci2mem[hose].lo, 0);  in mv64x60_config_pci_windows()
443 	out_le32((u32 *)(bridge_base + mv64x60_pci2mem[hose].size),mem_size);  in mv64x60_config_pci_windows()
446 	out_le32((u32 *)(bridge_base + mv64x60_pci_acc[hose][0].hi), 0);  in mv64x60_config_pci_windows()
447 	out_le32((u32 *)(bridge_base + mv64x60_pci_acc[hose][0].lo), acc_bits);  in mv64x60_config_pci_windows()
448 	out_le32((u32 *)(bridge_base + mv64x60_pci_acc[hose][0].size),mem_size);  in mv64x60_config_pci_windows()
454 	mv64x60_cfg_write(bridge_base, hose, bus, PCI_DEVFN(0,0),  in mv64x60_config_pci_windows()
455 			mv64x60_pci2reg[hose].hi, 0);  in mv64x60_config_pci_windows()
456 	mv64x60_cfg_write(bridge_base, hose, bus, PCI_DEVFN(0,0),  in mv64x60_config_pci_windows()
457 			mv64x60_pci2reg[hose].lo, i);  in mv64x60_config_pci_windows()
495 void mv64x60_config_cpu2pci_window(u8 *bridge_base, u8 hose, u32 pci_base_hi,  in mv64x60_config_cpu2pci_window()  argument
501 	out_le32((u32 *)(bridge_base + offset_tbl[hose].lo), cpu_base);  in mv64x60_config_cpu2pci_window()
503 	if (offset_tbl[hose].remap_hi != 0)  in mv64x60_config_cpu2pci_window()
504 		out_le32((u32 *)(bridge_base + offset_tbl[hose].remap_hi),  in mv64x60_config_cpu2pci_window()
506 	out_le32((u32 *)(bridge_base + offset_tbl[hose].remap_lo),  in mv64x60_config_cpu2pci_window()
510 	out_le32((u32 *)(bridge_base + offset_tbl[hose].size), size);  in mv64x60_config_cpu2pci_window()