181 u32 mv64x60_cfg_read(u8 *bridge_base, u8 hose, u8 bus, u8 devfn, u8 offset)  in mv64x60_cfg_read()  argument
183 	out_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].addr),  in mv64x60_cfg_read()
185 	return in_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].data));  in mv64x60_cfg_read()
188 void mv64x60_cfg_write(u8 *bridge_base, u8 hose, u8 bus, u8 devfn, u8 offset,  in mv64x60_cfg_write()  argument
191 	out_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].addr),  in mv64x60_cfg_write()
193 	out_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].data), val);  in mv64x60_cfg_write()
280 void mv64x60_config_ctlr_windows(u8 *bridge_base, u8 *bridge_pbase,  in mv64x60_config_ctlr_windows()  argument
286 	out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_BAR_ENABLE), 0x3f);  in mv64x60_config_ctlr_windows()
287 	out_le32((u32 *)(bridge_base + MV64x60_MPSC2MEM_BAR_ENABLE), 0xf);  in mv64x60_config_ctlr_windows()
288 	out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_BAR_ENABLE), 0xff);  in mv64x60_config_ctlr_windows()
293 	enables = in_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE)) & 0xf;  in mv64x60_config_ctlr_windows()
299 		base = in_le32((u32 *)(bridge_base + mv64x60_cpu2mem[i].lo))  in mv64x60_config_ctlr_windows()
302 		size = in_le32((u32 *)(bridge_base + mv64x60_cpu2mem[i].size))  in mv64x60_config_ctlr_windows()
306 		out_le32((u32 *)(bridge_base + mv64x60_enet2mem[i].lo), base);  in mv64x60_config_ctlr_windows()
307 		out_le32((u32 *)(bridge_base + mv64x60_enet2mem[i].size), size);  in mv64x60_config_ctlr_windows()
308 		out_le32((u32 *)(bridge_base + mv64x60_mpsc2mem[i].lo), base);  in mv64x60_config_ctlr_windows()
309 		out_le32((u32 *)(bridge_base + mv64x60_mpsc2mem[i].size), size);  in mv64x60_config_ctlr_windows()
310 		out_le32((u32 *)(bridge_base + mv64x60_idma2mem[i].lo), base);  in mv64x60_config_ctlr_windows()
311 		out_le32((u32 *)(bridge_base + mv64x60_idma2mem[i].size), size);  in mv64x60_config_ctlr_windows()
314 	out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_ACC_PROT_0), prot);  in mv64x60_config_ctlr_windows()
315 	out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_ACC_PROT_1), prot);  in mv64x60_config_ctlr_windows()
316 	out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_ACC_PROT_2), prot);  in mv64x60_config_ctlr_windows()
317 	out_le32((u32 *)(bridge_base + MV64x60_MPSC2MEM_ACC_PROT_0), prot);  in mv64x60_config_ctlr_windows()
318 	out_le32((u32 *)(bridge_base + MV64x60_MPSC2MEM_ACC_PROT_1), prot);  in mv64x60_config_ctlr_windows()
319 	out_le32((u32 *)(bridge_base + MV64x60_IDMA2MEM_ACC_PROT_0), prot);  in mv64x60_config_ctlr_windows()
320 	out_le32((u32 *)(bridge_base + MV64x60_IDMA2MEM_ACC_PROT_1), prot);  in mv64x60_config_ctlr_windows()
321 	out_le32((u32 *)(bridge_base + MV64x60_IDMA2MEM_ACC_PROT_2), prot);  in mv64x60_config_ctlr_windows()
322 	out_le32((u32 *)(bridge_base + MV64x60_IDMA2MEM_ACC_PROT_3), prot);  in mv64x60_config_ctlr_windows()
325 	out_le32((u32 *)(bridge_base + MV64x60_MPSC2REGS_BASE),  in mv64x60_config_ctlr_windows()
328 	out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_BAR_ENABLE), enables);  in mv64x60_config_ctlr_windows()
329 	out_le32((u32 *)(bridge_base + MV64x60_MPSC2MEM_BAR_ENABLE), enables);  in mv64x60_config_ctlr_windows()
330 	out_le32((u32 *)(bridge_base + MV64x60_IDMA2MEM_BAR_ENABLE), enables);  in mv64x60_config_ctlr_windows()
411 void mv64x60_config_pci_windows(u8 *bridge_base, u8 *bridge_pbase, u8 hose,  in mv64x60_config_pci_windows()  argument
419 	out_le32((u32 *)(bridge_base + bar_enable), enables);  in mv64x60_config_pci_windows()
422 		out_le32((u32 *)(bridge_base + mv64x60_pci_acc[hose][i].lo), 0);  in mv64x60_config_pci_windows()
431 	i = in_le32((u32 *)(bridge_base + offset));  in mv64x60_config_pci_windows()
432 	out_le32((u32 *)(bridge_base + offset), i & ~0x1);  in mv64x60_config_pci_windows()
437 	mv64x60_cfg_write(bridge_base, hose, bus,  in mv64x60_config_pci_windows()
440 	mv64x60_cfg_write(bridge_base, hose, bus,  in mv64x60_config_pci_windows()
443 	out_le32((u32 *)(bridge_base + mv64x60_pci2mem[hose].size),mem_size);  in mv64x60_config_pci_windows()
446 	out_le32((u32 *)(bridge_base + mv64x60_pci_acc[hose][0].hi), 0);  in mv64x60_config_pci_windows()
447 	out_le32((u32 *)(bridge_base + mv64x60_pci_acc[hose][0].lo), acc_bits);  in mv64x60_config_pci_windows()
448 	out_le32((u32 *)(bridge_base + mv64x60_pci_acc[hose][0].size),mem_size);  in mv64x60_config_pci_windows()
451 	i = (u32)bridge_base;  in mv64x60_config_pci_windows()
454 	mv64x60_cfg_write(bridge_base, hose, bus, PCI_DEVFN(0,0),  in mv64x60_config_pci_windows()
456 	mv64x60_cfg_write(bridge_base, hose, bus, PCI_DEVFN(0,0),  in mv64x60_config_pci_windows()
460 	out_le32((u32 *)(bridge_base + bar_enable), enables);  in mv64x60_config_pci_windows()
495 void mv64x60_config_cpu2pci_window(u8 *bridge_base, u8 hose, u32 pci_base_hi,  in mv64x60_config_cpu2pci_window()  argument
501 	out_le32((u32 *)(bridge_base + offset_tbl[hose].lo), cpu_base);  in mv64x60_config_cpu2pci_window()
504 		out_le32((u32 *)(bridge_base + offset_tbl[hose].remap_hi),  in mv64x60_config_cpu2pci_window()
506 	out_le32((u32 *)(bridge_base + offset_tbl[hose].remap_lo),  in mv64x60_config_cpu2pci_window()
510 	out_le32((u32 *)(bridge_base + offset_tbl[hose].size), size);  in mv64x60_config_cpu2pci_window()
514 u32 mv64x60_get_mem_size(u8 *bridge_base)  in mv64x60_get_mem_size()  argument
519 	enables = in_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE)) & 0xf;  in mv64x60_get_mem_size()
523 			v = in_le32((u32*)(bridge_base  in mv64x60_get_mem_size()