452 	unsigned long newbase = R1(regs->iir)?regs->gr[R1(regs->iir)]:0;  in handle_unaligned()
482 	switch (MAJOR_OP(regs->iir))  in handle_unaligned()
487 		if (regs->iir&0x20)  in handle_unaligned()
490 			if (regs->iir&0x1000)		/* short loads */  in handle_unaligned()
491 				if (regs->iir&0x200)  in handle_unaligned()
492 					newbase += IM5_3(regs->iir);  in handle_unaligned()
494 					newbase += IM5_2(regs->iir);  in handle_unaligned()
495 			else if (regs->iir&0x2000)	/* scaled indexed */  in handle_unaligned()
498 				switch (regs->iir & OPCODE1_MASK)  in handle_unaligned()
508 				newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0)<<shift;  in handle_unaligned()
510 				newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0);  in handle_unaligned()
516 		newbase += IM14(regs->iir);  in handle_unaligned()
520 		if (regs->iir&8)  in handle_unaligned()
523 			newbase += IM14(regs->iir&~0xe);  in handle_unaligned()
529 		newbase += IM14(regs->iir&6);  in handle_unaligned()
533 		if (regs->iir&4)  in handle_unaligned()
536 			newbase += IM14(regs->iir&~4);  in handle_unaligned()
542 	switch (regs->iir & OPCODE1_MASK)  in handle_unaligned()
546 		ret = emulate_ldh(regs, R3(regs->iir));  in handle_unaligned()
553 		ret = emulate_ldw(regs, R3(regs->iir),0);  in handle_unaligned()
557 		ret = emulate_sth(regs, R2(regs->iir));  in handle_unaligned()
562 		ret = emulate_stw(regs, R2(regs->iir),0);  in handle_unaligned()
570 		ret = emulate_ldd(regs, R3(regs->iir),0);  in handle_unaligned()
575 		ret = emulate_std(regs, R2(regs->iir),0);  in handle_unaligned()
584 		ret = emulate_ldw(regs,FR3(regs->iir),1);  in handle_unaligned()
590 		ret = emulate_ldd(regs,R3(regs->iir),1);  in handle_unaligned()
598 		ret = emulate_stw(regs,FR3(regs->iir),1);  in handle_unaligned()
604 		ret = emulate_std(regs,R3(regs->iir),1);  in handle_unaligned()
615 	switch (regs->iir & OPCODE2_MASK)  in handle_unaligned()
619 		ret = emulate_ldd(regs,R2(regs->iir),1);  in handle_unaligned()
623 		ret = emulate_std(regs, R2(regs->iir),1);  in handle_unaligned()
626 		ret = emulate_ldd(regs, R2(regs->iir),0);  in handle_unaligned()
629 		ret = emulate_std(regs, R2(regs->iir),0);  in handle_unaligned()
633 	switch (regs->iir & OPCODE3_MASK)  in handle_unaligned()
637 		ret = emulate_ldw(regs, R2(regs->iir),0);  in handle_unaligned()
640 		ret = emulate_ldw(regs, R2(regs->iir),1);  in handle_unaligned()
645 		ret = emulate_stw(regs, R2(regs->iir),1);  in handle_unaligned()
648 		ret = emulate_stw(regs, R2(regs->iir),0);  in handle_unaligned()
651 	switch (regs->iir & OPCODE4_MASK)  in handle_unaligned()
654 		ret = emulate_ldh(regs, R2(regs->iir));  in handle_unaligned()
658 		ret = emulate_ldw(regs, R2(regs->iir),0);  in handle_unaligned()
661 		ret = emulate_sth(regs, R2(regs->iir));  in handle_unaligned()
665 		ret = emulate_stw(regs, R2(regs->iir),0);  in handle_unaligned()
669 	if (ret == 0 && modify && R1(regs->iir))  in handle_unaligned()
670 		regs->gr[R1(regs->iir)] = newbase;  in handle_unaligned()
674 		printk(KERN_CRIT "Not-handled unaligned insn 0x%08lx\n", regs->iir);  in handle_unaligned()
730 	switch (regs->iir & OPCODE1_MASK) {  in check_unaligned()
748 		switch (regs->iir & OPCODE4_MASK) {  in check_unaligned()