Lines Matching refs:r6
60 #define EMERGENCY_PRINT_STORE_GPR6 l.sw 0x28(r0),r6
61 #define EMERGENCY_PRINT_LOAD_GPR6 l.lwz r6,0x28(r0)
91 #define EXCEPTION_STORE_GPR6 l.sw 0x74(r0),r6
92 #define EXCEPTION_LOAD_GPR6 l.lwz r6,0x74(r0)
460 CLEAR_GPR(r6)
527 LOAD_SYMBOL_2_GPR(r6,SPR_ITLBMR_BASE(0))
531 l.mtspr r6,r0,0x0
534 l.addi r6,r6,1
596 CLEAR_GPR(r6)
646 l.mfspr r6,r0,SPR_SR
649 l.and r5,r6,r5
673 l.addi r6,r0,0
679 l.mtspr r0,r6,SPR_ICBIR
680 l.sfne r6,r5
682 l.add r6,r6,r14
686 l.mfspr r6,r0,SPR_SR
687 l.ori r6,r6,SPR_SR_ICE
688 l.mtspr r0,r6,SPR_SR
712 l.mfspr r6,r0,SPR_SR
715 l.and r5,r6,r5
739 l.addi r6,r0,0
742 l.mtspr r0,r6,SPR_DCBIR
743 l.sfne r6,r5
745 l.add r6,r6,r14
748 l.mfspr r6,r0,SPR_SR
749 l.ori r6,r6,SPR_SR_DCE
750 l.mtspr r0,r6,SPR_SR
794 l.mfspr r6,r0,SPR_ESR_BASE //
795 l.andi r6,r6,SPR_SR_SM // are we in kernel mode ?
796 l.sfeqi r6,0 // r6 == 0x1 --> SM
814 CLEAR_GPR(r6)
818 l.mfspr r6, r0, SPR_DMMUCFGR
819 l.andi r6, r6, SPR_DMMUCFGR_NTS
820 l.srli r6, r6, SPR_DMMUCFGR_NTS_OFF
822 l.sll r5, r5, r6 // r5 = number DMMU sets
823 l.addi r6, r5, -1 // r6 = nsets mask
824 l.and r2, r3, r6 // r2 <- r3 % NSETS_MASK
826 l.or r6,r6,r4 // r6 <- r4
827 l.ori r6,r6,~(VPN_MASK) // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff
830 l.and r5,r5,r6 // r5 <- VPN :VPN .x001 - we have DTLBMR entry
834 LOAD_SYMBOL_2_GPR(r6,0xbfffffff)
835 l.sfgeu r6,r4 // flag if r6 >= r4 (if 0xbfffffff >= EA)
890 l.mfspr r6,r0,SPR_ESR_BASE //
891 l.andi r6,r6,SPR_SR_SM // are we in kernel mode ?
892 l.sfeqi r6,0 // r6 == 0x1 --> SM
901 CLEAR_GPR(r6)
905 l.mfspr r6, r0, SPR_IMMUCFGR
906 l.andi r6, r6, SPR_IMMUCFGR_NTS
907 l.srli r6, r6, SPR_IMMUCFGR_NTS_OFF
909 l.sll r5, r5, r6 // r5 = number IMMU sets from IMMUCFGR
910 l.addi r6, r5, -1 // r6 = nsets mask
911 l.and r2, r3, r6 // r2 <- r3 % NSETS_MASK
913 l.or r6,r6,r4 // r6 <- r4
914 l.ori r6,r6,~(VPN_MASK) // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff
917 l.and r5,r5,r6 // r5 <- VPN :VPN .x001 - we have ITLBMR entry
927 LOAD_SYMBOL_2_GPR(r6,0x0fffffff)
928 l.sfgeu r6,r4 // flag if r6 >= r4 (if 0xb0ffffff >= EA)
1029 l.mfspr r6, r0, SPR_DMMUCFGR
1030 l.andi r6, r6, SPR_DMMUCFGR_NTS
1031 l.srli r6, r6, SPR_DMMUCFGR_NTS_OFF
1033 l.sll r3, r3, r6 // r3 = number DMMU sets DMMUCFGR
1034 l.addi r6, r3, -1 // r6 = nsets mask
1035 l.and r5, r5, r6 // calc offset: & (NUM_TLB_ENTRIES-1)
1140 l.mfspr r6, r0, SPR_IMMUCFGR
1141 l.andi r6, r6, SPR_IMMUCFGR_NTS
1142 l.srli r6, r6, SPR_IMMUCFGR_NTS_OFF
1144 l.sll r3, r3, r6 // r3 = number IMMU sets IMMUCFGR
1145 l.addi r6, r3, -1 // r6 = nsets mask
1146 l.and r5, r5, r6 // calc offset: & (NUM_TLB_ENTRIES-1)
1213 tophys(r6,r2)
1225 l.lwz r4,0x0(r6) // load op @ EEA + 0x0 (fc address)
1227 l.lwz r4,-0x4(r6) // load op @ EEA - 0x4 (f8 address)
1263 l.addi r6,r2,0x4 // this is 0xaaaabbbb
1268 l.srli r5,r6,16
1274 l.andi r5,r6,0xffff
1281 l.slli r6,r4,6 // original offset shifted left 6 - 2
1294 l.add r5,r6,r5 // orig_off + (old_jump - new_jump)
1314 l.addi r6,r2,0x4 // this is 0xaaaabbbb
1319 l.srli r5,r6,16
1325 l.andi r5,r6,0xffff
1343 l.slli r6,r4,6 // original offset shifted left 6 - 2
1355 l.add r6,r6,r4 // (orig_off + old_jump)
1356 l.sub r6,r6,r5 // (orig_off + old_jump) - new_jump
1357 l.srli r6,r6,6 // new offset shifted right 2
1364 l.or r6,r4,r6 // l.b(n)f new offset
1365 l.sw TRAMP_SLOT_2(r3),r6 // write it back
1431 l.addi r6,r0,0x20
1434 l.sfeq r5,r6
1440 l.addi r6,r0,0x60
1443 l.sfeq r5,r6
1499 l.addi r6,r0,0x20
1502 l.sfeq r5,r6
1508 l.addi r6,r0,0x60
1511 l.sfeq r5,r6