Lines Matching refs:__SYSREG
11 #define ASB2364_FPGA_REG_RESET_LAN __SYSREG(0xa9001300, u16)
12 #define ASB2364_FPGA_REG_RESET_UART __SYSREG(0xa9001304, u16)
13 #define ASB2364_FPGA_REG_RESET_I2C __SYSREG(0xa9001308, u16)
14 #define ASB2364_FPGA_REG_RESET_USB __SYSREG(0xa900130c, u16)
15 #define ASB2364_FPGA_REG_RESET_AV __SYSREG(0xa9001310, u16)
17 #define ASB2364_FPGA_REG_IRQ(X) __SYSREG(0xa9001510+((X)*4), u16)
24 #define ASB2364_FPGA_REG_MASK(X) __SYSREG(0xa9001590+((X)*4), u16)
31 #define ASB2364_FPGA_REG_CPLD5_SET1 __SYSREG(0xa9002500, u16)
32 #define ASB2364_FPGA_REG_CPLD5_SET2 __SYSREG(0xa9002504, u16)
33 #define ASB2364_FPGA_REG_CPLD6_SET1 __SYSREG(0xa9002600, u16)
34 #define ASB2364_FPGA_REG_CPLD6_SET2 __SYSREG(0xa9002604, u16)
35 #define ASB2364_FPGA_REG_CPLD7_SET1 __SYSREG(0xa9002700, u16)
36 #define ASB2364_FPGA_REG_CPLD7_SET2 __SYSREG(0xa9002704, u16)
37 #define ASB2364_FPGA_REG_CPLD8_SET1 __SYSREG(0xa9002800, u16)
38 #define ASB2364_FPGA_REG_CPLD8_SET2 __SYSREG(0xa9002804, u16)
39 #define ASB2364_FPGA_REG_CPLD9_SET1 __SYSREG(0xa9002900, u16)
40 #define ASB2364_FPGA_REG_CPLD9_SET2 __SYSREG(0xa9002904, u16)
41 #define ASB2364_FPGA_REG_CPLD10_SET1 __SYSREG(0xa9002a00, u16)
42 #define ASB2364_FPGA_REG_CPLD10_SET2 __SYSREG(0xa9002a04, u16)