38 	mace->perif.ctrl.misc;  in flush_mace_bus()
185 	mace->pci.control = macepci_mask;  in enable_macepci_irq()
196 	mace->pci.control = macepci_mask;  in disable_macepci_irq()
266 	mace->perif.ctrl.imask = maceisa_mask;  in enable_maceisa_irq()
283 	mace->perif.ctrl.imask = maceisa_mask;  in disable_maceisa_irq()
292 	mace_int = mace->perif.ctrl.istat;  in mask_and_ack_maceisa_irq()
294 	mace->perif.ctrl.istat = mace_int;  in mask_and_ack_maceisa_irq()
348 	printk("MACE ISA intr mask: %08lx\n", mace->perif.ctrl.imask);  in ip32_unknown_interrupt()
349 	printk("MACE ISA intr status: %08lx\n", mace->perif.ctrl.istat);  in ip32_unknown_interrupt()
350 	printk("MACE PCI control register: %08x\n", mace->pci.control);  in ip32_unknown_interrupt()
384 		unsigned long mace_int = mace->perif.ctrl.istat;  in ip32_irq0()
444 	mace->perif.ctrl.istat = 0;  in arch_init_irq()
445 	mace->perif.ctrl.imask = 0;  in arch_init_irq()