Lines Matching refs:s
179 pescx_cfg_rd.s.addr = cfg_offset; in cvmx_pcie_cfgx_read()
182 return pescx_cfg_rd.s.data; in cvmx_pcie_cfgx_read()
186 pemx_cfg_rd.s.addr = cfg_offset; in cvmx_pcie_cfgx_read()
189 return pemx_cfg_rd.s.data; in cvmx_pcie_cfgx_read()
207 pescx_cfg_wr.s.addr = cfg_offset; in cvmx_pcie_cfgx_write()
208 pescx_cfg_wr.s.data = val; in cvmx_pcie_cfgx_write()
213 pemx_cfg_wr.s.addr = cfg_offset; in cvmx_pcie_cfgx_write()
214 pemx_cfg_wr.s.data = val; in cvmx_pcie_cfgx_write()
238 if ((bus <= pciercx_cfg006.s.pbnum) && (dev != 0)) in __cvmx_pcie_build_config_addr()
248 pcie_addr.config.ty = (bus > pciercx_cfg006.s.pbnum); in __cvmx_pcie_build_config_addr()
406 pciercx_cfg030.s.mps = MPS_CN5XXX; in __cvmx_pcie_rc_initialize_config_space()
407 pciercx_cfg030.s.mrrs = MRRS_CN5XXX; in __cvmx_pcie_rc_initialize_config_space()
409 pciercx_cfg030.s.mps = MPS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space()
410 pciercx_cfg030.s.mrrs = MRRS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space()
416 pciercx_cfg030.s.ro_en = 1; in __cvmx_pcie_rc_initialize_config_space()
418 pciercx_cfg030.s.ns_en = 1; in __cvmx_pcie_rc_initialize_config_space()
420 pciercx_cfg030.s.ce_en = 1; in __cvmx_pcie_rc_initialize_config_space()
422 pciercx_cfg030.s.nfe_en = 1; in __cvmx_pcie_rc_initialize_config_space()
424 pciercx_cfg030.s.fe_en = 1; in __cvmx_pcie_rc_initialize_config_space()
426 pciercx_cfg030.s.ur_en = 1; in __cvmx_pcie_rc_initialize_config_space()
440 npei_ctl_status2.s.mps = MPS_CN5XXX; in __cvmx_pcie_rc_initialize_config_space()
442 npei_ctl_status2.s.mrrs = MRRS_CN5XXX; in __cvmx_pcie_rc_initialize_config_space()
444 npei_ctl_status2.s.c1_b1_s = 3; /* Port1 BAR1 Size 256MB */ in __cvmx_pcie_rc_initialize_config_space()
446 npei_ctl_status2.s.c0_b1_s = 3; /* Port0 BAR1 Size 256MB */ in __cvmx_pcie_rc_initialize_config_space()
459 prt_cfg.s.mps = MPS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space()
460 prt_cfg.s.mrrs = MRRS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space()
462 prt_cfg.s.molr = 32; in __cvmx_pcie_rc_initialize_config_space()
466 sli_s2m_portx_ctl.s.mrrs = MRRS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space()
472 pciercx_cfg070.s.ge = 1; /* ECRC generation enable. */ in __cvmx_pcie_rc_initialize_config_space()
473 pciercx_cfg070.s.ce = 1; /* ECRC check enable. */ in __cvmx_pcie_rc_initialize_config_space()
483 pciercx_cfg001.s.msae = 1; /* Memory space enable. */ in __cvmx_pcie_rc_initialize_config_space()
484 pciercx_cfg001.s.me = 1; /* Bus master enable. */ in __cvmx_pcie_rc_initialize_config_space()
485 pciercx_cfg001.s.i_dis = 1; /* INTx assertion disable. */ in __cvmx_pcie_rc_initialize_config_space()
486 pciercx_cfg001.s.see = 1; /* SERR# enable */ in __cvmx_pcie_rc_initialize_config_space()
498 pciercx_cfg032.s.aslpc = 0; /* Active state Link PM control. */ in __cvmx_pcie_rc_initialize_config_space()
511 pciercx_cfg006.s.pbnum = 1; in __cvmx_pcie_rc_initialize_config_space()
512 pciercx_cfg006.s.sbnum = 1; in __cvmx_pcie_rc_initialize_config_space()
513 pciercx_cfg006.s.subbnum = 1; in __cvmx_pcie_rc_initialize_config_space()
523 pciercx_cfg008.s.mb_addr = 0x100; in __cvmx_pcie_rc_initialize_config_space()
524 pciercx_cfg008.s.ml_addr = 0; in __cvmx_pcie_rc_initialize_config_space()
537 pciercx_cfg009.s.lmem_base = 0x100; in __cvmx_pcie_rc_initialize_config_space()
538 pciercx_cfg009.s.lmem_limit = 0; in __cvmx_pcie_rc_initialize_config_space()
539 pciercx_cfg010.s.umem_base = 0x100; in __cvmx_pcie_rc_initialize_config_space()
540 pciercx_cfg011.s.umem_limit = 0; in __cvmx_pcie_rc_initialize_config_space()
550 pciercx_cfg035.s.secee = 1; /* System error on correctable error enable. */ in __cvmx_pcie_rc_initialize_config_space()
551 pciercx_cfg035.s.sefee = 1; /* System error on fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
552 pciercx_cfg035.s.senfee = 1; /* System error on non-fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
553 pciercx_cfg035.s.pmeie = 1; /* PME interrupt enable. */ in __cvmx_pcie_rc_initialize_config_space()
561 pciercx_cfg075.s.cere = 1; /* Correctable error reporting enable. */ in __cvmx_pcie_rc_initialize_config_space()
562 pciercx_cfg075.s.nfere = 1; /* Non-fatal error reporting enable. */ in __cvmx_pcie_rc_initialize_config_space()
563 pciercx_cfg075.s.fere = 1; /* Fatal error reporting enable. */ in __cvmx_pcie_rc_initialize_config_space()
571 pciercx_cfg034.s.hpint_en = 1; /* Hot-plug interrupt enable. */ in __cvmx_pcie_rc_initialize_config_space()
572 pciercx_cfg034.s.dlls_en = 1; /* Data Link Layer state changed enable */ in __cvmx_pcie_rc_initialize_config_space()
573 pciercx_cfg034.s.ccint_en = 1; /* Command completed interrupt enable. */ in __cvmx_pcie_rc_initialize_config_space()
597 if (pescx_ctl_status.s.qlm_cfg == 0) in __cvmx_pcie_rc_initialize_link_gen1()
599 pciercx_cfg452.s.lme = 0xf; in __cvmx_pcie_rc_initialize_link_gen1()
602 pciercx_cfg452.s.lme = 0x7; in __cvmx_pcie_rc_initialize_link_gen1()
613 pciercx_cfg455.s.m_cpl_len_err = 1; in __cvmx_pcie_rc_initialize_link_gen1()
619 pescx_ctl_status.s.lane_swp = 1; in __cvmx_pcie_rc_initialize_link_gen1()
625 pescx_ctl_status.s.lnk_enb = 1; in __cvmx_pcie_rc_initialize_link_gen1()
644 } while (pciercx_cfg032.s.dlla == 0); in __cvmx_pcie_rc_initialize_link_gen1()
658 switch (pciercx_cfg032.s.nlw) { in __cvmx_pcie_rc_initialize_link_gen1()
660 pciercx_cfg448.s.rtl = 1677; in __cvmx_pcie_rc_initialize_link_gen1()
663 pciercx_cfg448.s.rtl = 867; in __cvmx_pcie_rc_initialize_link_gen1()
666 pciercx_cfg448.s.rtl = 462; in __cvmx_pcie_rc_initialize_link_gen1()
669 pciercx_cfg448.s.rtl = 258; in __cvmx_pcie_rc_initialize_link_gen1()
715 if ((pcie_port == 0) && !npei_ctl_status.s.host_mode) { in __cvmx_pcie_rc_initialize_gen1()
736 npei_ctl_status.s.arb = 1; in __cvmx_pcie_rc_initialize_gen1()
738 npei_ctl_status.s.cfg_rtry = 0x20; in __cvmx_pcie_rc_initialize_gen1()
744 npei_ctl_status.s.p0_ntags = 0x20; in __cvmx_pcie_rc_initialize_gen1()
745 npei_ctl_status.s.p1_ntags = 0x20; in __cvmx_pcie_rc_initialize_gen1()
766 if (ciu_soft_prst.s.soft_prst == 0) { in __cvmx_pcie_rc_initialize_gen1()
768 ciu_soft_prst.s.soft_prst = 1; in __cvmx_pcie_rc_initialize_gen1()
771 ciu_soft_prst.s.soft_prst = 1; in __cvmx_pcie_rc_initialize_gen1()
777 ciu_soft_prst.s.soft_prst = 0; in __cvmx_pcie_rc_initialize_gen1()
780 ciu_soft_prst.s.soft_prst = 0; in __cvmx_pcie_rc_initialize_gen1()
798 if (ciu_soft_prst.s.soft_prst == 0) { in __cvmx_pcie_rc_initialize_gen1()
800 ciu_soft_prst.s.soft_prst = 1; in __cvmx_pcie_rc_initialize_gen1()
810 ciu_soft_prst.s.soft_prst = 0; in __cvmx_pcie_rc_initialize_gen1()
814 ciu_soft_prst.s.soft_prst = 0; in __cvmx_pcie_rc_initialize_gen1()
833 pescx_ctl_status2.s.pclk_run = 1; in __cvmx_pcie_rc_initialize_gen1()
851 if (pescx_ctl_status2.s.pcierst) { in __cvmx_pcie_rc_initialize_gen1()
886 npei_mem_access_ctl.s.max_word = 0; /* Allow 16 words to combine */ in __cvmx_pcie_rc_initialize_gen1()
887 npei_mem_access_ctl.s.timer = 127; /* Wait up to 127 cycles for more data */ in __cvmx_pcie_rc_initialize_gen1()
892 mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */ in __cvmx_pcie_rc_initialize_gen1()
893 mem_access_subid.s.nmerge = 1; /* Due to an errata on pass 1 chips, no merging is allowed. */ in __cvmx_pcie_rc_initialize_gen1()
894 mem_access_subid.s.esr = 1; /* Endian-swap for Reads. */ in __cvmx_pcie_rc_initialize_gen1()
895 mem_access_subid.s.esw = 1; /* Endian-swap for Writes. */ in __cvmx_pcie_rc_initialize_gen1()
896 …mem_access_subid.s.nsr = 0; /* Enable Snooping for Reads. Octeon doesn't care, but devices might w… in __cvmx_pcie_rc_initialize_gen1()
897 mem_access_subid.s.nsw = 0; /* Enable Snoop for Writes. */ in __cvmx_pcie_rc_initialize_gen1()
898 mem_access_subid.s.ror = 0; /* Disable Relaxed Ordering for Reads. */ in __cvmx_pcie_rc_initialize_gen1()
899 mem_access_subid.s.row = 0; /* Disable Relaxed Ordering for Writes. */ in __cvmx_pcie_rc_initialize_gen1()
900 mem_access_subid.s.ba = 0; /* PCIe Adddress Bits <63:34>. */ in __cvmx_pcie_rc_initialize_gen1()
908 mem_access_subid.s.ba += 1; /* Set each SUBID to extend the addressable range */ in __cvmx_pcie_rc_initialize_gen1()
928 bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22); in __cvmx_pcie_rc_initialize_gen1()
929 bar1_index.s.ca = 1; /* Not Cached */ in __cvmx_pcie_rc_initialize_gen1()
930 bar1_index.s.end_swp = 1; /* Endian Swap mode */ in __cvmx_pcie_rc_initialize_gen1()
931 bar1_index.s.addr_v = 1; /* Valid entry */ in __cvmx_pcie_rc_initialize_gen1()
946 bar1_index.s.addr_idx += (((1ull << 28) / 16ull) >> 22); in __cvmx_pcie_rc_initialize_gen1()
969 npei_ctl_port.s.bar2_enb = 1; in __cvmx_pcie_rc_initialize_gen1()
970 npei_ctl_port.s.bar2_esx = 1; in __cvmx_pcie_rc_initialize_gen1()
971 npei_ctl_port.s.bar2_cax = 0; in __cvmx_pcie_rc_initialize_gen1()
972 npei_ctl_port.s.ptlp_ro = 1; in __cvmx_pcie_rc_initialize_gen1()
973 npei_ctl_port.s.ctlp_ro = 1; in __cvmx_pcie_rc_initialize_gen1()
974 npei_ctl_port.s.wait_com = 0; in __cvmx_pcie_rc_initialize_gen1()
975 npei_ctl_port.s.waitl_com = 0; in __cvmx_pcie_rc_initialize_gen1()
980 npei_ctl_port.s.bar2_enb = 1; in __cvmx_pcie_rc_initialize_gen1()
981 npei_ctl_port.s.bar2_esx = 1; in __cvmx_pcie_rc_initialize_gen1()
982 npei_ctl_port.s.bar2_cax = 0; in __cvmx_pcie_rc_initialize_gen1()
983 npei_ctl_port.s.ptlp_ro = 1; in __cvmx_pcie_rc_initialize_gen1()
984 npei_ctl_port.s.ctlp_ro = 1; in __cvmx_pcie_rc_initialize_gen1()
985 npei_ctl_port.s.wait_com = 0; in __cvmx_pcie_rc_initialize_gen1()
986 npei_ctl_port.s.waitl_com = 0; in __cvmx_pcie_rc_initialize_gen1()
1035 old_in_fif_p_count = dbg_data.s.data & 0xff; in __cvmx_pcie_rc_initialize_gen1()
1039 in_fif_p_count = dbg_data.s.data & 0xff; in __cvmx_pcie_rc_initialize_gen1()
1049 out_p_count = (dbg_data.s.data>>1) & 0xff; in __cvmx_pcie_rc_initialize_gen1()
1077 cvmx_dprintf("PCIe: Port %d link active, %d lanes\n", pcie_port, pciercx_cfg032.s.nlw); in __cvmx_pcie_rc_initialize_gen1()
1100 pem_ctl_status.s.lnk_enb = 1; in __cvmx_pcie_rc_initialize_link_gen2()
1110 } while ((pciercx_cfg032.s.dlla == 0) || (pciercx_cfg032.s.lt == 1)); in __cvmx_pcie_rc_initialize_link_gen2()
1121 switch (pciercx_cfg032.s.nlw) { in __cvmx_pcie_rc_initialize_link_gen2()
1123 pciercx_cfg448.s.rtl = 1677; in __cvmx_pcie_rc_initialize_link_gen2()
1126 pciercx_cfg448.s.rtl = 867; in __cvmx_pcie_rc_initialize_link_gen2()
1129 pciercx_cfg448.s.rtl = 462; in __cvmx_pcie_rc_initialize_link_gen2()
1132 pciercx_cfg448.s.rtl = 258; in __cvmx_pcie_rc_initialize_link_gen2()
1177 if (qlmx_cfg.s.qlm_spd == 15) { in __cvmx_pcie_rc_initialize_gen2()
1182 switch (qlmx_cfg.s.qlm_spd) { in __cvmx_pcie_rc_initialize_gen2()
1206 if (sriox_status_reg.s.srio) { in __cvmx_pcie_rc_initialize_gen2()
1234 if (!mio_rst_ctl.s.host_mode) { in __cvmx_pcie_rc_initialize_gen2()
1244 ciu_qlm.s.txbypass = 1; in __cvmx_pcie_rc_initialize_gen2()
1245 ciu_qlm.s.txdeemph = 5; in __cvmx_pcie_rc_initialize_gen2()
1246 ciu_qlm.s.txmargin = 0x17; in __cvmx_pcie_rc_initialize_gen2()
1251 ciu_qlm.s.txbypass = 1; in __cvmx_pcie_rc_initialize_gen2()
1252 ciu_qlm.s.txdeemph = 5; in __cvmx_pcie_rc_initialize_gen2()
1253 ciu_qlm.s.txmargin = 0x17; in __cvmx_pcie_rc_initialize_gen2()
1267 if (ciu_soft_prst.s.soft_prst == 0) { in __cvmx_pcie_rc_initialize_gen2()
1269 ciu_soft_prst.s.soft_prst = 1; in __cvmx_pcie_rc_initialize_gen2()
1279 ciu_soft_prst.s.soft_prst = 0; in __cvmx_pcie_rc_initialize_gen2()
1283 ciu_soft_prst.s.soft_prst = 0; in __cvmx_pcie_rc_initialize_gen2()
1316 pciercx_cfg515.s.dsc = 1; in __cvmx_pcie_rc_initialize_gen2()
1328 pciercx_cfg031.s.mls = 1; in __cvmx_pcie_rc_initialize_gen2()
1338 sli_mem_access_ctl.s.max_word = 0; /* Allow 16 words to combine */ in __cvmx_pcie_rc_initialize_gen2()
1339 sli_mem_access_ctl.s.timer = 127; /* Wait up to 127 cycles for more data */ in __cvmx_pcie_rc_initialize_gen2()
1344 mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */ in __cvmx_pcie_rc_initialize_gen2()
1345 mem_access_subid.s.nmerge = 0; /* Allow merging as it works on CN6XXX. */ in __cvmx_pcie_rc_initialize_gen2()
1346 mem_access_subid.s.esr = 1; /* Endian-swap for Reads. */ in __cvmx_pcie_rc_initialize_gen2()
1347 mem_access_subid.s.esw = 1; /* Endian-swap for Writes. */ in __cvmx_pcie_rc_initialize_gen2()
1348 mem_access_subid.s.wtype = 0; /* "No snoop" and "Relaxed ordering" are not set */ in __cvmx_pcie_rc_initialize_gen2()
1349 mem_access_subid.s.rtype = 0; /* "No snoop" and "Relaxed ordering" are not set */ in __cvmx_pcie_rc_initialize_gen2()
1395 pemx_bar_ctl.s.bar1_siz = 3; /* 256MB BAR1*/ in __cvmx_pcie_rc_initialize_gen2()
1396 pemx_bar_ctl.s.bar2_enb = 1; in __cvmx_pcie_rc_initialize_gen2()
1397 pemx_bar_ctl.s.bar2_esx = 1; in __cvmx_pcie_rc_initialize_gen2()
1398 pemx_bar_ctl.s.bar2_cax = 0; in __cvmx_pcie_rc_initialize_gen2()
1401 sli_ctl_portx.s.ptlp_ro = 1; in __cvmx_pcie_rc_initialize_gen2()
1402 sli_ctl_portx.s.ctlp_ro = 1; in __cvmx_pcie_rc_initialize_gen2()
1403 sli_ctl_portx.s.wait_com = 0; in __cvmx_pcie_rc_initialize_gen2()
1404 sli_ctl_portx.s.waitl_com = 0; in __cvmx_pcie_rc_initialize_gen2()
1411 bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22); in __cvmx_pcie_rc_initialize_gen2()
1412 bar1_index.s.ca = 1; /* Not Cached */ in __cvmx_pcie_rc_initialize_gen2()
1413 bar1_index.s.end_swp = 1; /* Endian Swap mode */ in __cvmx_pcie_rc_initialize_gen2()
1414 bar1_index.s.addr_v = 1; /* Valid entry */ in __cvmx_pcie_rc_initialize_gen2()
1419 bar1_index.s.addr_idx += (((1ull << 28) / 16ull) >> 22); in __cvmx_pcie_rc_initialize_gen2()
1427 pemx_ctl_status.s.cfg_rtry = 250 * 5000000 / 0x10000; in __cvmx_pcie_rc_initialize_gen2()
1432 …rt %d link active, %d lanes, speed gen%d\n", pcie_port, pciercx_cfg032.s.nlw, pciercx_cfg032.s.ls); in __cvmx_pcie_rc_initialize_gen2()
1510 pemx_ctl.s.cfg_rtry = retry_cnt; in set_cfg_read_retry()
1521 retry_cnt = pemx_ctl.s.cfg_rtry; in disable_cfg_read_retry()
1522 pemx_ctl.s.cfg_rtry = 0; in disable_cfg_read_retry()
1531 if (pemx_int_sum.s.crs_dr) in is_cfg_retry()
1565 if (pciercx_cfg006.s.pbnum != bus_number) { in octeon_pcie_read_config()
1566 pciercx_cfg006.s.pbnum = bus_number; in octeon_pcie_read_config()
1567 pciercx_cfg006.s.sbnum = bus_number; in octeon_pcie_read_config()
1568 pciercx_cfg006.s.subbnum = bus_number; in octeon_pcie_read_config()
1663 cvmmemctl.s.didtto = 2; in octeon_pcie_read_config()
1910 host_mode = npei_ctl_status.s.host_mode; in octeon_pcie_setup()
1915 host_mode = mio_rst_ctl.s.host_mode; in octeon_pcie_setup()
1925 if (sriox_status_reg.s.srio) { in octeon_pcie_setup()
1989 host_mode = mio_rst_ctl.s.host_mode; in octeon_pcie_setup()
1998 if (sriox_status_reg.s.srio) { in octeon_pcie_setup()
2072 sli_ctl_portx.s.inta_map = 1; in octeon_pcie_setup()
2073 sli_ctl_portx.s.intb_map = 1; in octeon_pcie_setup()
2074 sli_ctl_portx.s.intc_map = 1; in octeon_pcie_setup()
2075 sli_ctl_portx.s.intd_map = 1; in octeon_pcie_setup()
2079 sli_ctl_portx.s.inta_map = 0; in octeon_pcie_setup()
2080 sli_ctl_portx.s.intb_map = 0; in octeon_pcie_setup()
2081 sli_ctl_portx.s.intc_map = 0; in octeon_pcie_setup()
2082 sli_ctl_portx.s.intd_map = 0; in octeon_pcie_setup()