707 	union cvmx_npei_bar1_indexx bar1_index;  in __cvmx_pcie_rc_initialize_gen1()  local
927 	bar1_index.u32 = 0;  in __cvmx_pcie_rc_initialize_gen1()
928 	bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22);  in __cvmx_pcie_rc_initialize_gen1()
929 	bar1_index.s.ca = 1;	   /* Not Cached */  in __cvmx_pcie_rc_initialize_gen1()
930 	bar1_index.s.end_swp = 1;  /* Endian Swap mode */  in __cvmx_pcie_rc_initialize_gen1()
931 	bar1_index.s.addr_v = 1;   /* Valid entry */  in __cvmx_pcie_rc_initialize_gen1()
943 				    bar1_index.u32);  in __cvmx_pcie_rc_initialize_gen1()
946 		bar1_index.s.addr_idx += (((1ull << 28) / 16ull) >> 22);  in __cvmx_pcie_rc_initialize_gen1()
1164 	union cvmx_pemx_bar1_indexx bar1_index;  in __cvmx_pcie_rc_initialize_gen2()  local
1410 	bar1_index.u64 = 0;  in __cvmx_pcie_rc_initialize_gen2()
1411 	bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22);  in __cvmx_pcie_rc_initialize_gen2()
1412 	bar1_index.s.ca = 1;	   /* Not Cached */  in __cvmx_pcie_rc_initialize_gen2()
1413 	bar1_index.s.end_swp = 1;  /* Endian Swap mode */  in __cvmx_pcie_rc_initialize_gen2()
1414 	bar1_index.s.addr_v = 1;   /* Valid entry */  in __cvmx_pcie_rc_initialize_gen2()
1417 		cvmx_write_csr(CVMX_PEMX_BAR1_INDEXX(i, pcie_port), bar1_index.u64);  in __cvmx_pcie_rc_initialize_gen2()
1419 		bar1_index.s.addr_idx += (((1ull << 28) / 16ull) >> 22);  in __cvmx_pcie_rc_initialize_gen2()