Lines Matching refs:t1
61 mfcr t1, t0
64 or t1, t1, t2
65 mtcr t1, t0
68 mfcr t1, t0
69 ori t1, 0x1000 /* Enable Icache partitioning */
70 mtcr t1, t0
73 lui t1, 0x0100 /* Disable BRU accepting ALU ops */
74 mtcr t1, t0
84 li t1, (1 << 29) /* ELPA bit */
85 or t0, t1
97 slt t1, t0, 0x1200
98 beqz t1, 15f
103 li t1, LSU_DEBUG_ADDR
110 mtcr v1, t1
112 mfcr v1, t1
118 mtcr v1, t1
120 mfcr v1, t1
133 li t1, 0x80010000
136 bne t0, t1, 16b
176 li t1, 0x1500 /* XLP 9xx */
177 beq t0, t1, 2f /* does not need to set coherent */
180 li t1, 0x1300 /* XLP 5xx */
181 beq t0, t1, 2f /* does not need to set coherent */
186 mfc0 t1, CP0_EBASE, 1
187 srl t1, 5
188 andi t1, 0x3 /* t1 <- node */
190 mul t3, t2, t1 /* t3 = node * 0x40000 */
193 li t1, 0x1
194 sll t0, t1, t0
198 lw t1, 0(t2)
199 and t1, t1, t0
200 sw t1, 0(t2)
203 lw t1, 0(t2)
222 lw t1, BOOT_THREAD_MODE(t0) /* t1 <- thread mode */
225 or t2, t2, t1
248 lw t1, BOOT_THREAD_MODE(t0) /* t1 <- thread mode */
249 subu t1, 0x3 /* 4-thread per core mode? */
250 bnez t1, 2f
254 li t1, 0x55
255 mtcr t1, t0
262 move t1, zero
264 ori t1, ST0_KX
266 mtc0 t1, CP0_STATUS
272 ADDIU t1, t3, BOOT_CPU_READY
274 PTR_ADDU t1, v1
276 sw t2, 0(t1)