Lines Matching refs:t0
60 li t0, LSU_DEFEATURE
61 mfcr t1, t0
65 mtcr t1, t0
67 li t0, ICU_DEFEATURE
68 mfcr t1, t0
70 mtcr t1, t0
72 li t0, SCHED_DEFEATURE
74 mtcr t1, t0
83 mfc0 t0, CP0_PAGEMASK, 1
85 or t0, t1
86 mtc0 t0, CP0_PAGEMASK, 1
95 mfc0 t0, CP0_EBASE, 0
96 andi t0, t0, PRID_IMP_MASK
97 slt t1, t0, 0x1200
102 li t0, LSU_DEBUG_DATA0
108 mtcr zero, t0
116 mtcr zero, t0
132 li t0, 0x80000000
134 16: cache Index_Writeback_Inv_D, 0(t0)
135 addiu t0, t0, 32
136 bne t0, t1, 16b
174 mfc0 t0, CP0_EBASE, 0 /* processor ID */
175 andi t0, PRID_IMP_MASK
177 beq t0, t1, 2f /* does not need to set coherent */
181 beq t0, t1, 2f /* does not need to set coherent */
185 mfc0 t0, CP0_EBASE, 1
191 srl t0, t0, 2
192 and t0, t0, 0x7 /* t0 <- core */
194 sll t0, t1, t0
195 nor t0, t0, zero /* t0 <- ~(1 << core) */
199 and t1, t1, t0
221 li t0, CKSEG1ADDR(RESET_DATA_PHYS)
222 lw t1, BOOT_THREAD_MODE(t0) /* t1 <- thread mode */
223 li t0, ((CPU_BLOCKID_MAP << 8) | MAP_THREADMODE)
224 mfcr t2, t0
226 mtcr t2, t0
247 li t0, CKSEG1ADDR(RESET_DATA_PHYS)
248 lw t1, BOOT_THREAD_MODE(t0) /* t1 <- thread mode */
253 li t0, IFU_BRUB_RESERVE
255 mtcr t1, t0