Lines Matching refs:a0
57 EX sdc1 $f1, SC_FPREGS+8(a0)
58 EX sdc1 $f3, SC_FPREGS+24(a0)
59 EX sdc1 $f5, SC_FPREGS+40(a0)
60 EX sdc1 $f7, SC_FPREGS+56(a0)
61 EX sdc1 $f9, SC_FPREGS+72(a0)
62 EX sdc1 $f11, SC_FPREGS+88(a0)
63 EX sdc1 $f13, SC_FPREGS+104(a0)
64 EX sdc1 $f15, SC_FPREGS+120(a0)
65 EX sdc1 $f17, SC_FPREGS+136(a0)
66 EX sdc1 $f19, SC_FPREGS+152(a0)
67 EX sdc1 $f21, SC_FPREGS+168(a0)
68 EX sdc1 $f23, SC_FPREGS+184(a0)
69 EX sdc1 $f25, SC_FPREGS+200(a0)
70 EX sdc1 $f27, SC_FPREGS+216(a0)
71 EX sdc1 $f29, SC_FPREGS+232(a0)
72 EX sdc1 $f31, SC_FPREGS+248(a0)
79 EX sdc1 $f0, SC_FPREGS+0(a0)
80 EX sdc1 $f2, SC_FPREGS+16(a0)
81 EX sdc1 $f4, SC_FPREGS+32(a0)
82 EX sdc1 $f6, SC_FPREGS+48(a0)
83 EX sdc1 $f8, SC_FPREGS+64(a0)
84 EX sdc1 $f10, SC_FPREGS+80(a0)
85 EX sdc1 $f12, SC_FPREGS+96(a0)
86 EX sdc1 $f14, SC_FPREGS+112(a0)
87 EX sdc1 $f16, SC_FPREGS+128(a0)
88 EX sdc1 $f18, SC_FPREGS+144(a0)
89 EX sdc1 $f20, SC_FPREGS+160(a0)
90 EX sdc1 $f22, SC_FPREGS+176(a0)
91 EX sdc1 $f24, SC_FPREGS+192(a0)
92 EX sdc1 $f26, SC_FPREGS+208(a0)
93 EX sdc1 $f28, SC_FPREGS+224(a0)
94 EX sdc1 $f30, SC_FPREGS+240(a0)
95 EX sw t1, SC_FPC_CSR(a0)
117 EX sdc1 $f1, SC32_FPREGS+8(a0)
118 EX sdc1 $f3, SC32_FPREGS+24(a0)
119 EX sdc1 $f5, SC32_FPREGS+40(a0)
120 EX sdc1 $f7, SC32_FPREGS+56(a0)
121 EX sdc1 $f9, SC32_FPREGS+72(a0)
122 EX sdc1 $f11, SC32_FPREGS+88(a0)
123 EX sdc1 $f13, SC32_FPREGS+104(a0)
124 EX sdc1 $f15, SC32_FPREGS+120(a0)
125 EX sdc1 $f17, SC32_FPREGS+136(a0)
126 EX sdc1 $f19, SC32_FPREGS+152(a0)
127 EX sdc1 $f21, SC32_FPREGS+168(a0)
128 EX sdc1 $f23, SC32_FPREGS+184(a0)
129 EX sdc1 $f25, SC32_FPREGS+200(a0)
130 EX sdc1 $f27, SC32_FPREGS+216(a0)
131 EX sdc1 $f29, SC32_FPREGS+232(a0)
132 EX sdc1 $f31, SC32_FPREGS+248(a0)
135 1: EX sdc1 $f0, SC32_FPREGS+0(a0)
136 EX sdc1 $f2, SC32_FPREGS+16(a0)
137 EX sdc1 $f4, SC32_FPREGS+32(a0)
138 EX sdc1 $f6, SC32_FPREGS+48(a0)
139 EX sdc1 $f8, SC32_FPREGS+64(a0)
140 EX sdc1 $f10, SC32_FPREGS+80(a0)
141 EX sdc1 $f12, SC32_FPREGS+96(a0)
142 EX sdc1 $f14, SC32_FPREGS+112(a0)
143 EX sdc1 $f16, SC32_FPREGS+128(a0)
144 EX sdc1 $f18, SC32_FPREGS+144(a0)
145 EX sdc1 $f20, SC32_FPREGS+160(a0)
146 EX sdc1 $f22, SC32_FPREGS+176(a0)
147 EX sdc1 $f24, SC32_FPREGS+192(a0)
148 EX sdc1 $f26, SC32_FPREGS+208(a0)
149 EX sdc1 $f28, SC32_FPREGS+224(a0)
150 EX sdc1 $f30, SC32_FPREGS+240(a0)
151 EX sw t1, SC32_FPC_CSR(a0)
153 EX sw t0, SC32_FPC_EIR(a0)
167 EX lw t1, SC_FPC_CSR(a0)
181 EX ldc1 $f1, SC_FPREGS+8(a0)
182 EX ldc1 $f3, SC_FPREGS+24(a0)
183 EX ldc1 $f5, SC_FPREGS+40(a0)
184 EX ldc1 $f7, SC_FPREGS+56(a0)
185 EX ldc1 $f9, SC_FPREGS+72(a0)
186 EX ldc1 $f11, SC_FPREGS+88(a0)
187 EX ldc1 $f13, SC_FPREGS+104(a0)
188 EX ldc1 $f15, SC_FPREGS+120(a0)
189 EX ldc1 $f17, SC_FPREGS+136(a0)
190 EX ldc1 $f19, SC_FPREGS+152(a0)
191 EX ldc1 $f21, SC_FPREGS+168(a0)
192 EX ldc1 $f23, SC_FPREGS+184(a0)
193 EX ldc1 $f25, SC_FPREGS+200(a0)
194 EX ldc1 $f27, SC_FPREGS+216(a0)
195 EX ldc1 $f29, SC_FPREGS+232(a0)
196 EX ldc1 $f31, SC_FPREGS+248(a0)
201 EX ldc1 $f0, SC_FPREGS+0(a0)
202 EX ldc1 $f2, SC_FPREGS+16(a0)
203 EX ldc1 $f4, SC_FPREGS+32(a0)
204 EX ldc1 $f6, SC_FPREGS+48(a0)
205 EX ldc1 $f8, SC_FPREGS+64(a0)
206 EX ldc1 $f10, SC_FPREGS+80(a0)
207 EX ldc1 $f12, SC_FPREGS+96(a0)
208 EX ldc1 $f14, SC_FPREGS+112(a0)
209 EX ldc1 $f16, SC_FPREGS+128(a0)
210 EX ldc1 $f18, SC_FPREGS+144(a0)
211 EX ldc1 $f20, SC_FPREGS+160(a0)
212 EX ldc1 $f22, SC_FPREGS+176(a0)
213 EX ldc1 $f24, SC_FPREGS+192(a0)
214 EX ldc1 $f26, SC_FPREGS+208(a0)
215 EX ldc1 $f28, SC_FPREGS+224(a0)
216 EX ldc1 $f30, SC_FPREGS+240(a0)
228 EX lw t1, SC32_FPC_CSR(a0)
237 EX ldc1 $f1, SC32_FPREGS+8(a0)
238 EX ldc1 $f3, SC32_FPREGS+24(a0)
239 EX ldc1 $f5, SC32_FPREGS+40(a0)
240 EX ldc1 $f7, SC32_FPREGS+56(a0)
241 EX ldc1 $f9, SC32_FPREGS+72(a0)
242 EX ldc1 $f11, SC32_FPREGS+88(a0)
243 EX ldc1 $f13, SC32_FPREGS+104(a0)
244 EX ldc1 $f15, SC32_FPREGS+120(a0)
245 EX ldc1 $f17, SC32_FPREGS+136(a0)
246 EX ldc1 $f19, SC32_FPREGS+152(a0)
247 EX ldc1 $f21, SC32_FPREGS+168(a0)
248 EX ldc1 $f23, SC32_FPREGS+184(a0)
249 EX ldc1 $f25, SC32_FPREGS+200(a0)
250 EX ldc1 $f27, SC32_FPREGS+216(a0)
251 EX ldc1 $f29, SC32_FPREGS+232(a0)
252 EX ldc1 $f31, SC32_FPREGS+248(a0)
254 1: EX ldc1 $f0, SC32_FPREGS+0(a0)
255 EX ldc1 $f2, SC32_FPREGS+16(a0)
256 EX ldc1 $f4, SC32_FPREGS+32(a0)
257 EX ldc1 $f6, SC32_FPREGS+48(a0)
258 EX ldc1 $f8, SC32_FPREGS+64(a0)
259 EX ldc1 $f10, SC32_FPREGS+80(a0)
260 EX ldc1 $f12, SC32_FPREGS+96(a0)
261 EX ldc1 $f14, SC32_FPREGS+112(a0)
262 EX ldc1 $f16, SC32_FPREGS+128(a0)
263 EX ldc1 $f18, SC32_FPREGS+144(a0)
264 EX ldc1 $f20, SC32_FPREGS+160(a0)
265 EX ldc1 $f22, SC32_FPREGS+176(a0)
266 EX ldc1 $f24, SC32_FPREGS+192(a0)
267 EX ldc1 $f26, SC32_FPREGS+208(a0)
268 EX ldc1 $f28, SC32_FPREGS+224(a0)
269 EX ldc1 $f30, SC32_FPREGS+240(a0)