69 		T  = 0,  enumerator
74 	#define T  macro
814 	[PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
815 	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x02, CNTR_EVEN, T },
816 	[PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },
823 	[PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
824 	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x27, CNTR_EVEN, T },
825 	[PERF_COUNT_HW_BRANCH_MISSES] = { 0x27, CNTR_ODD, T },
847 	[PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, T },
848 	[PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
849 	[PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },
874 		[C(RESULT_ACCESS)]	= { 0x0a, CNTR_EVEN, T },
875 		[C(RESULT_MISS)]	= { 0x0b, CNTR_EVEN | CNTR_ODD, T },
878 		[C(RESULT_ACCESS)]	= { 0x0a, CNTR_EVEN, T },
879 		[C(RESULT_MISS)]	= { 0x0b, CNTR_EVEN | CNTR_ODD, T },
884 		[C(RESULT_ACCESS)]	= { 0x09, CNTR_EVEN, T },
885 		[C(RESULT_MISS)]	= { 0x09, CNTR_ODD, T },
888 		[C(RESULT_ACCESS)]	= { 0x09, CNTR_EVEN, T },
889 		[C(RESULT_MISS)]	= { 0x09, CNTR_ODD, T },
892 		[C(RESULT_ACCESS)]	= { 0x14, CNTR_EVEN, T },
911 		[C(RESULT_ACCESS)]	= { 0x06, CNTR_EVEN, T },
912 		[C(RESULT_MISS)]	= { 0x06, CNTR_ODD, T },
915 		[C(RESULT_ACCESS)]	= { 0x06, CNTR_EVEN, T },
916 		[C(RESULT_MISS)]	= { 0x06, CNTR_ODD, T },
921 		[C(RESULT_ACCESS)]	= { 0x05, CNTR_EVEN, T },
922 		[C(RESULT_MISS)]	= { 0x05, CNTR_ODD, T },
925 		[C(RESULT_ACCESS)]	= { 0x05, CNTR_EVEN, T },
926 		[C(RESULT_MISS)]	= { 0x05, CNTR_ODD, T },
932 		[C(RESULT_ACCESS)]	= { 0x02, CNTR_EVEN, T },
933 		[C(RESULT_MISS)]	= { 0x02, CNTR_ODD, T },
936 		[C(RESULT_ACCESS)]	= { 0x02, CNTR_EVEN, T },
937 		[C(RESULT_MISS)]	= { 0x02, CNTR_ODD, T },
955 		[C(RESULT_ACCESS)]	= { 0x17, CNTR_ODD, T },
956 		[C(RESULT_MISS)]	= { 0x18, CNTR_ODD, T },
959 		[C(RESULT_ACCESS)]	= { 0x17, CNTR_ODD, T },
960 		[C(RESULT_MISS)]	= { 0x18, CNTR_ODD, T },
965 		[C(RESULT_ACCESS)]	= { 0x06, CNTR_EVEN, T },
966 		[C(RESULT_MISS)]	= { 0x06, CNTR_ODD, T },
969 		[C(RESULT_ACCESS)]	= { 0x06, CNTR_EVEN, T },
970 		[C(RESULT_MISS)]	= { 0x06, CNTR_ODD, T },
973 		[C(RESULT_ACCESS)]	= { 0x34, CNTR_EVEN, T },
997 		[C(RESULT_ACCESS)]	= { 0x04, CNTR_EVEN, T },
998 		[C(RESULT_MISS)]	= { 0x04, CNTR_ODD, T },
1001 		[C(RESULT_ACCESS)]	= { 0x04, CNTR_EVEN, T },
1002 		[C(RESULT_MISS)]	= { 0x04, CNTR_ODD, T },
1008 		[C(RESULT_ACCESS)]	= { 0x27, CNTR_EVEN, T },
1009 		[C(RESULT_MISS)]	= { 0x27, CNTR_ODD, T },
1012 		[C(RESULT_ACCESS)]	= { 0x27, CNTR_EVEN, T },
1013 		[C(RESULT_MISS)]	= { 0x27, CNTR_ODD, T },
1086 		[C(RESULT_ACCESS)]	= { 12, CNTR_EVEN, T },
1087 		[C(RESULT_MISS)]	= { 12, CNTR_ODD, T },
1090 		[C(RESULT_ACCESS)]	= { 12, CNTR_EVEN, T },
1091 		[C(RESULT_MISS)]	= { 12, CNTR_ODD, T },
1096 		[C(RESULT_ACCESS)]	= { 10, CNTR_EVEN, T },
1097 		[C(RESULT_MISS)]	= { 10, CNTR_ODD, T },
1100 		[C(RESULT_ACCESS)]	= { 10, CNTR_EVEN, T },
1101 		[C(RESULT_MISS)]	= { 10, CNTR_ODD, T },
1104 		[C(RESULT_ACCESS)]	= { 23, CNTR_EVEN, T },
1124 		[C(RESULT_MISS)]	= { 0x02, CNTR_ODD, T },
1127 		[C(RESULT_MISS)]	= { 0x02, CNTR_ODD, T },
1534 			raw_event.range = T;  in mipsxx_pmu_map_raw_event()
1583 			raw_event.range = T;  in mipsxx_pmu_map_raw_event()
1598 			raw_event.range = T;  in mipsxx_pmu_map_raw_event()