Lines Matching refs:C
83 #define C(x) PERF_COUNT_HW_CACHE_##x macro
866 [C(L1D)] = {
873 [C(OP_READ)] = {
874 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
875 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
877 [C(OP_WRITE)] = {
878 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
879 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
882 [C(L1I)] = {
883 [C(OP_READ)] = {
884 [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T },
885 [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T },
887 [C(OP_WRITE)] = {
888 [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T },
889 [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T },
891 [C(OP_PREFETCH)] = {
892 [C(RESULT_ACCESS)] = { 0x14, CNTR_EVEN, T },
899 [C(LL)] = {
900 [C(OP_READ)] = {
901 [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P },
902 [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P },
904 [C(OP_WRITE)] = {
905 [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P },
906 [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P },
909 [C(DTLB)] = {
910 [C(OP_READ)] = {
911 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
912 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
914 [C(OP_WRITE)] = {
915 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
916 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
919 [C(ITLB)] = {
920 [C(OP_READ)] = {
921 [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T },
922 [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T },
924 [C(OP_WRITE)] = {
925 [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T },
926 [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T },
929 [C(BPU)] = {
931 [C(OP_READ)] = {
932 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T },
933 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
935 [C(OP_WRITE)] = {
936 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T },
937 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
947 [C(L1D)] = {
954 [C(OP_READ)] = {
955 [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T },
956 [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T },
958 [C(OP_WRITE)] = {
959 [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T },
960 [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T },
963 [C(L1I)] = {
964 [C(OP_READ)] = {
965 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
966 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
968 [C(OP_WRITE)] = {
969 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
970 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
972 [C(OP_PREFETCH)] = {
973 [C(RESULT_ACCESS)] = { 0x34, CNTR_EVEN, T },
980 [C(LL)] = {
981 [C(OP_READ)] = {
982 [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P },
983 [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN, P },
985 [C(OP_WRITE)] = {
986 [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P },
987 [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN, P },
995 [C(ITLB)] = {
996 [C(OP_READ)] = {
997 [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T },
998 [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T },
1000 [C(OP_WRITE)] = {
1001 [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T },
1002 [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T },
1005 [C(BPU)] = {
1007 [C(OP_READ)] = {
1008 [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T },
1009 [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T },
1011 [C(OP_WRITE)] = {
1012 [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T },
1013 [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T },
1022 [C(L1D)] = {
1029 [C(OP_READ)] = {
1030 [C(RESULT_MISS)] = { 0x04, CNTR_ODD },
1032 [C(OP_WRITE)] = {
1033 [C(RESULT_MISS)] = { 0x04, CNTR_ODD },
1036 [C(L1I)] = {
1037 [C(OP_READ)] = {
1038 [C(RESULT_MISS)] = { 0x04, CNTR_EVEN },
1040 [C(OP_WRITE)] = {
1041 [C(RESULT_MISS)] = { 0x04, CNTR_EVEN },
1044 [C(DTLB)] = {
1045 [C(OP_READ)] = {
1046 [C(RESULT_MISS)] = { 0x09, CNTR_ODD },
1048 [C(OP_WRITE)] = {
1049 [C(RESULT_MISS)] = { 0x09, CNTR_ODD },
1052 [C(ITLB)] = {
1053 [C(OP_READ)] = {
1054 [C(RESULT_MISS)] = { 0x0c, CNTR_ODD },
1056 [C(OP_WRITE)] = {
1057 [C(RESULT_MISS)] = { 0x0c, CNTR_ODD },
1060 [C(BPU)] = {
1062 [C(OP_READ)] = {
1063 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN },
1064 [C(RESULT_MISS)] = { 0x02, CNTR_ODD },
1066 [C(OP_WRITE)] = {
1067 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN },
1068 [C(RESULT_MISS)] = { 0x02, CNTR_ODD },
1078 [C(L1D)] = {
1085 [C(OP_READ)] = {
1086 [C(RESULT_ACCESS)] = { 12, CNTR_EVEN, T },
1087 [C(RESULT_MISS)] = { 12, CNTR_ODD, T },
1089 [C(OP_WRITE)] = {
1090 [C(RESULT_ACCESS)] = { 12, CNTR_EVEN, T },
1091 [C(RESULT_MISS)] = { 12, CNTR_ODD, T },
1094 [C(L1I)] = {
1095 [C(OP_READ)] = {
1096 [C(RESULT_ACCESS)] = { 10, CNTR_EVEN, T },
1097 [C(RESULT_MISS)] = { 10, CNTR_ODD, T },
1099 [C(OP_WRITE)] = {
1100 [C(RESULT_ACCESS)] = { 10, CNTR_EVEN, T },
1101 [C(RESULT_MISS)] = { 10, CNTR_ODD, T },
1103 [C(OP_PREFETCH)] = {
1104 [C(RESULT_ACCESS)] = { 23, CNTR_EVEN, T },
1111 [C(LL)] = {
1112 [C(OP_READ)] = {
1113 [C(RESULT_ACCESS)] = { 28, CNTR_EVEN, P },
1114 [C(RESULT_MISS)] = { 28, CNTR_ODD, P },
1116 [C(OP_WRITE)] = {
1117 [C(RESULT_ACCESS)] = { 28, CNTR_EVEN, P },
1118 [C(RESULT_MISS)] = { 28, CNTR_ODD, P },
1121 [C(BPU)] = {
1123 [C(OP_READ)] = {
1124 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
1126 [C(OP_WRITE)] = {
1127 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
1137 [C(L1D)] = {
1138 [C(OP_READ)] = {
1139 [C(RESULT_ACCESS)] = { 0x2b, CNTR_ALL },
1140 [C(RESULT_MISS)] = { 0x2e, CNTR_ALL },
1142 [C(OP_WRITE)] = {
1143 [C(RESULT_ACCESS)] = { 0x30, CNTR_ALL },
1146 [C(L1I)] = {
1147 [C(OP_READ)] = {
1148 [C(RESULT_ACCESS)] = { 0x18, CNTR_ALL },
1150 [C(OP_PREFETCH)] = {
1151 [C(RESULT_ACCESS)] = { 0x19, CNTR_ALL },
1154 [C(DTLB)] = {
1159 [C(OP_READ)] = {
1160 [C(RESULT_MISS)] = { 0x35, CNTR_ALL },
1162 [C(OP_WRITE)] = {
1163 [C(RESULT_MISS)] = { 0x35, CNTR_ALL },
1166 [C(ITLB)] = {
1167 [C(OP_READ)] = {
1168 [C(RESULT_MISS)] = { 0x37, CNTR_ALL },
1177 [C(L1D)] = {
1178 [C(OP_READ)] = {
1179 [C(RESULT_ACCESS)] = { 0x31, CNTR_ALL }, /* PAPI_L1_DCR */
1180 [C(RESULT_MISS)] = { 0x30, CNTR_ALL }, /* PAPI_L1_LDM */
1182 [C(OP_WRITE)] = {
1183 [C(RESULT_ACCESS)] = { 0x2f, CNTR_ALL }, /* PAPI_L1_DCW */
1184 [C(RESULT_MISS)] = { 0x2e, CNTR_ALL }, /* PAPI_L1_STM */
1187 [C(L1I)] = {
1188 [C(OP_READ)] = {
1189 [C(RESULT_ACCESS)] = { 0x04, CNTR_ALL }, /* PAPI_L1_ICA */
1190 [C(RESULT_MISS)] = { 0x07, CNTR_ALL }, /* PAPI_L1_ICM */
1193 [C(LL)] = {
1194 [C(OP_READ)] = {
1195 [C(RESULT_ACCESS)] = { 0x35, CNTR_ALL }, /* PAPI_L2_DCR */
1196 [C(RESULT_MISS)] = { 0x37, CNTR_ALL }, /* PAPI_L2_LDM */
1198 [C(OP_WRITE)] = {
1199 [C(RESULT_ACCESS)] = { 0x34, CNTR_ALL }, /* PAPI_L2_DCA */
1200 [C(RESULT_MISS)] = { 0x36, CNTR_ALL }, /* PAPI_L2_DCM */
1203 [C(DTLB)] = {
1208 [C(OP_READ)] = {
1209 [C(RESULT_MISS)] = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */
1211 [C(OP_WRITE)] = {
1212 [C(RESULT_MISS)] = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */
1215 [C(ITLB)] = {
1216 [C(OP_READ)] = {
1217 [C(RESULT_MISS)] = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */
1219 [C(OP_WRITE)] = {
1220 [C(RESULT_MISS)] = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */
1223 [C(BPU)] = {
1224 [C(OP_READ)] = {
1225 [C(RESULT_MISS)] = { 0x25, CNTR_ALL },