907 	unsigned long vaddr;  in mipsr2_decoder()  local
1200 		vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);  in mipsr2_decoder()
1201 		if (!access_ok(VERIFY_READ, vaddr, 4)) {  in mipsr2_decoder()
1202 			current->thread.cp0_baduaddr = vaddr;  in mipsr2_decoder()
1261 			  "+&r"(vaddr), "+&r"(err)  in mipsr2_decoder()
1273 		vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);  in mipsr2_decoder()
1274 		if (!access_ok(VERIFY_READ, vaddr, 4)) {  in mipsr2_decoder()
1275 			current->thread.cp0_baduaddr = vaddr;  in mipsr2_decoder()
1336 			  "+&r"(vaddr), "+&r"(err)  in mipsr2_decoder()
1347 		vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);  in mipsr2_decoder()
1348 		if (!access_ok(VERIFY_WRITE, vaddr, 4)) {  in mipsr2_decoder()
1349 			current->thread.cp0_baduaddr = vaddr;  in mipsr2_decoder()
1407 			  "+&r"(vaddr), "+&r"(err)  in mipsr2_decoder()
1417 		vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);  in mipsr2_decoder()
1418 		if (!access_ok(VERIFY_WRITE, vaddr, 4)) {  in mipsr2_decoder()
1419 			current->thread.cp0_baduaddr = vaddr;  in mipsr2_decoder()
1477 			  "+&r"(vaddr), "+&r"(err)  in mipsr2_decoder()
1492 		vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);  in mipsr2_decoder()
1493 		if (!access_ok(VERIFY_READ, vaddr, 8)) {  in mipsr2_decoder()
1494 			current->thread.cp0_baduaddr = vaddr;  in mipsr2_decoder()
1596 			  "+&r"(vaddr), "+&r"(err)  in mipsr2_decoder()
1611 		vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);  in mipsr2_decoder()
1612 		if (!access_ok(VERIFY_READ, vaddr, 8)) {  in mipsr2_decoder()
1613 			current->thread.cp0_baduaddr = vaddr;  in mipsr2_decoder()
1715 			  "+&r"(vaddr), "+&r"(err)  in mipsr2_decoder()
1730 		vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);  in mipsr2_decoder()
1731 		if (!access_ok(VERIFY_WRITE, vaddr, 8)) {  in mipsr2_decoder()
1732 			current->thread.cp0_baduaddr = vaddr;  in mipsr2_decoder()
1834 			  "+&r"(vaddr), "+&r"(err)  in mipsr2_decoder()
1848 		vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);  in mipsr2_decoder()
1849 		if (!access_ok(VERIFY_WRITE, vaddr, 8)) {  in mipsr2_decoder()
1850 			current->thread.cp0_baduaddr = vaddr;  in mipsr2_decoder()
1952 			  "+&r"(vaddr), "+&r"(err)  in mipsr2_decoder()
1960 		vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);  in mipsr2_decoder()
1961 		if (vaddr & 0x3) {  in mipsr2_decoder()
1962 			current->thread.cp0_baduaddr = vaddr;  in mipsr2_decoder()
1966 		if (!access_ok(VERIFY_READ, vaddr, 4)) {  in mipsr2_decoder()
1967 			current->thread.cp0_baduaddr = vaddr;  in mipsr2_decoder()
2006 			: "r"(vaddr), "i"(SIGSEGV)  in mipsr2_decoder()
2016 		vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);  in mipsr2_decoder()
2017 		if (vaddr & 0x3) {  in mipsr2_decoder()
2018 			current->thread.cp0_baduaddr = vaddr;  in mipsr2_decoder()
2022 		if (!access_ok(VERIFY_WRITE, vaddr, 4)) {  in mipsr2_decoder()
2023 			current->thread.cp0_baduaddr = vaddr;  in mipsr2_decoder()
2064 			: "r"(vaddr), "i"(SIGSEGV));  in mipsr2_decoder()
2079 		vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);  in mipsr2_decoder()
2080 		if (vaddr & 0x7) {  in mipsr2_decoder()
2081 			current->thread.cp0_baduaddr = vaddr;  in mipsr2_decoder()
2085 		if (!access_ok(VERIFY_READ, vaddr, 8)) {  in mipsr2_decoder()
2086 			current->thread.cp0_baduaddr = vaddr;  in mipsr2_decoder()
2125 			: "r"(vaddr), "i"(SIGSEGV)  in mipsr2_decoder()
2140 		vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);  in mipsr2_decoder()
2141 		if (vaddr & 0x7) {  in mipsr2_decoder()
2142 			current->thread.cp0_baduaddr = vaddr;  in mipsr2_decoder()
2146 		if (!access_ok(VERIFY_WRITE, vaddr, 8)) {  in mipsr2_decoder()
2147 			current->thread.cp0_baduaddr = vaddr;  in mipsr2_decoder()
2188 			: "r"(vaddr), "i"(SIGSEGV));  in mipsr2_decoder()