Lines Matching refs:MSCIC_WRITE
24 #define MSCIC_WRITE(reg, data) do { *(volatile u32 *)(reg) = data; } while (0) macro
35 MSCIC_WRITE(MSC01_IC_DISL, 1<<(irq - irq_base)); in mask_msc_irq()
37 MSCIC_WRITE(MSC01_IC_DISH, 1<<(irq - irq_base - 32)); in mask_msc_irq()
46 MSCIC_WRITE(MSC01_IC_ENAL, 1<<(irq - irq_base)); in unmask_msc_irq()
48 MSCIC_WRITE(MSC01_IC_ENAH, 1<<(irq - irq_base - 32)); in unmask_msc_irq()
58 MSCIC_WRITE(MSC01_IC_EOI, 0); in level_mask_and_ack_msc_irq()
70 MSCIC_WRITE(MSC01_IC_EOI, 0); in edge_mask_and_ack_msc_irq()
74 MSCIC_WRITE(MSC01_IC_SUP+irq*8, r | ~MSC01_IC_SUP_EDGE_BIT); in edge_mask_and_ack_msc_irq()
75 MSCIC_WRITE(MSC01_IC_SUP+irq*8, r); in edge_mask_and_ack_msc_irq()
97 MSCIC_WRITE(MSC01_IC_RAMW, in msc_bind_eic_interrupt()
125 MSCIC_WRITE(MSC01_IC_RST, MSC01_IC_RST_RST_BIT); in init_msc_irqs()
139 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT); in init_msc_irqs()
141 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl); in init_msc_irqs()
149 MSCIC_WRITE(MSC01_IC_SUP+n*8, 0); in init_msc_irqs()
151 MSCIC_WRITE(MSC01_IC_SUP+n*8, imp->im_lvl); in init_msc_irqs()
157 MSCIC_WRITE(MSC01_IC_GENA, MSC01_IC_GENA_GENA_BIT); /* Enable interrupt generation */ in init_msc_irqs()