Lines Matching refs:t1
94 li t1, 2
95 sllv t0, t1, t0
98 _EXT t1, v0, MIPS_CONF1_IS_SHF, MIPS_CONF1_IS_SZ
99 xori t2, t1, 0x7
102 addiu t1, t1, 1
103 sllv t1, t3, t1
107 mul t1, t1, t0
108 mul t1, t1, t2
111 add a1, a0, t1
121 li t1, 2
122 sllv t0, t1, t0
125 _EXT t1, v0, MIPS_CONF1_DS_SHF, MIPS_CONF1_DS_SZ
126 xori t2, t1, 0x7
129 addiu t1, t1, 1
130 sllv t1, t3, t1
134 mul t1, t1, t0
135 mul t1, t1, t2
138 addu a1, a0, t1
181 lw t1, VPEBOOTCFG_PC(v0)
184 jr t1
240 la t1, 1f
241 jr.hb t1
271 sll t1, t5, VPECONF0_XTC_SHIFT
272 or t0, t0, t1
306 li t1, COREBOOTCFG_SIZE
307 mul t0, t0, t1
308 la t1, mips_cps_core_bootcfg
309 lw t1, 0(t1)
310 addu t0, t0, t1
317 mfc0 t1, CP0_MVPCONF0
318 srl t1, t1, MVPCONF0_PVPE_SHIFT
319 andi t1, t1, MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT
320 addiu t1, t1, 1
323 clz t1, t1
325 subu t1, t2, t1
327 sll t1, t2, t1
328 addiu t1, t1, -1
332 and t9, t9, t1
335 li t1, VPEBOOTCFG_SIZE
336 mul v0, t9, t1
354 la t1, 1f
355 jr.hb t1
357 1: mfc0 t1, CP0_MVPCONTROL
358 ori t1, t1, MVPCONTROL_VPC
359 mtc0 t1, CP0_MVPCONTROL
391 lw t1, VPEBOOTCFG_PC(t0)
392 mttc0 t1, CP0_TCRESTART
395 lw t1, VPEBOOTCFG_SP(t0)
396 mttgpr t1, sp
399 lw t1, VPEBOOTCFG_GP(t0)
400 mttgpr t1, gp
412 li t1, ~TCSTATUS_IXMT
413 and t0, t0, t1
432 mfc0 t1, CP0_MVPCONTROL
433 xori t1, t1, MVPCONTROL_VPC
434 mtc0 t1, CP0_MVPCONTROL
480 psstate t1
488 psstate t1