75 #define CHIP_TO_REG(chip, reg) (gpio_chip_to_jz_gpio_chip(chip)->base + (reg))  argument
207 static int jz_gpio_get_value(struct gpio_chip *chip, unsigned gpio)  in jz_gpio_get_value()  argument
209 	return !!(readl(CHIP_TO_REG(chip, JZ_REG_GPIO_PIN)) & BIT(gpio));  in jz_gpio_get_value()
212 static void jz_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)  in jz_gpio_set_value()  argument
214 	uint32_t __iomem *reg = CHIP_TO_REG(chip, JZ_REG_GPIO_DATA_SET);  in jz_gpio_set_value()
219 static int jz_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,  in jz_gpio_direction_output()  argument
222 	writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_SET));  in jz_gpio_direction_output()
223 	jz_gpio_set_value(chip, gpio, value);  in jz_gpio_direction_output()
228 static int jz_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)  in jz_gpio_direction_input()  argument
230 	writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_CLEAR));  in jz_gpio_direction_input()
280 static void jz_gpio_check_trigger_both(struct jz_gpio_chip *chip, unsigned int irq)  in jz_gpio_check_trigger_both()  argument
286 	if (!(chip->edge_trigger_both & mask))  in jz_gpio_check_trigger_both()
289 	reg = chip->base;  in jz_gpio_check_trigger_both()
291 	value = readl(chip->base + JZ_REG_GPIO_PIN);  in jz_gpio_check_trigger_both()
304 	struct jz_gpio_chip *chip = irq_desc_get_handler_data(desc);  in jz_gpio_irq_demux_handler()  local
306 	flag = readl(chip->base + JZ_REG_GPIO_FLAG);  in jz_gpio_irq_demux_handler()
310 	gpio_irq = chip->irq_base + __fls(flag);  in jz_gpio_irq_demux_handler()
312 	jz_gpio_check_trigger_both(chip, gpio_irq);  in jz_gpio_irq_demux_handler()
319 	struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);  in jz_gpio_set_irq_bit()  local
320 	writel(IRQ_TO_BIT(data->irq), chip->base + reg);  in jz_gpio_set_irq_bit()
325 	struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);  in jz_gpio_irq_unmask()  local
327 	jz_gpio_check_trigger_both(chip, data->irq);  in jz_gpio_irq_unmask()
350 	struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);  in jz_gpio_irq_set_type()  local
354 		uint32_t value = readl(chip->base + JZ_REG_GPIO_PIN);  in jz_gpio_irq_set_type()
359 		chip->edge_trigger_both |= IRQ_TO_BIT(irq);  in jz_gpio_irq_set_type()
361 		chip->edge_trigger_both &= ~IRQ_TO_BIT(irq);  in jz_gpio_irq_set_type()
390 	struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);  in jz_gpio_irq_set_wake()  local
393 	irq_set_irq_wake(chip->irq, on);  in jz_gpio_irq_set_wake()
419 static void jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id)  in jz4740_gpio_chip_init()  argument
424 	chip->base = ioremap(JZ4740_GPIO_BASE_ADDR + (id * 0x100), 0x100);  in jz4740_gpio_chip_init()
426 	chip->irq = JZ4740_IRQ_INTC_GPIO(id);  in jz4740_gpio_chip_init()
427 	irq_set_handler_data(chip->irq, chip);  in jz4740_gpio_chip_init()
428 	irq_set_chained_handler(chip->irq, jz_gpio_irq_demux_handler);  in jz4740_gpio_chip_init()
430 	gc = irq_alloc_generic_chip(chip->gpio_chip.label, 1, chip->irq_base,  in jz4740_gpio_chip_init()
431 		chip->base, handle_level_irq);  in jz4740_gpio_chip_init()
433 	gc->wake_enabled = IRQ_MSK(chip->gpio_chip.ngpio);  in jz4740_gpio_chip_init()
434 	gc->private = chip;  in jz4740_gpio_chip_init()
441 	ct->chip.name = "GPIO";  in jz4740_gpio_chip_init()
442 	ct->chip.irq_mask = irq_gc_mask_disable_reg;  in jz4740_gpio_chip_init()
443 	ct->chip.irq_unmask = jz_gpio_irq_unmask;  in jz4740_gpio_chip_init()
444 	ct->chip.irq_ack = irq_gc_ack_set_bit;  in jz4740_gpio_chip_init()
445 	ct->chip.irq_suspend = jz4740_irq_suspend;  in jz4740_gpio_chip_init()
446 	ct->chip.irq_resume = jz4740_irq_resume;  in jz4740_gpio_chip_init()
447 	ct->chip.irq_startup = jz_gpio_irq_startup;  in jz4740_gpio_chip_init()
448 	ct->chip.irq_shutdown = jz_gpio_irq_shutdown;  in jz4740_gpio_chip_init()
449 	ct->chip.irq_set_type = jz_gpio_irq_set_type;  in jz4740_gpio_chip_init()
450 	ct->chip.irq_set_wake = jz_gpio_irq_set_wake;  in jz4740_gpio_chip_init()
451 	ct->chip.flags = IRQCHIP_SET_TYPE_MASKED;  in jz4740_gpio_chip_init()
453 	irq_setup_generic_chip(gc, IRQ_MSK(chip->gpio_chip.ngpio),  in jz4740_gpio_chip_init()
456 	gpiochip_add(&chip->gpio_chip);  in jz4740_gpio_chip_init()
474 static inline void gpio_seq_reg(struct seq_file *s, struct jz_gpio_chip *chip,  in gpio_seq_reg()  argument
477 	seq_printf(s, "\t%s: %08x\n", name, readl(chip->base + reg));  in gpio_seq_reg()
482 	struct jz_gpio_chip *chip = jz4740_gpio_chips;  in gpio_regs_show()  local
485 	for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i, ++chip) {  in gpio_regs_show()
487 		gpio_seq_reg(s, chip, "Pin", JZ_REG_GPIO_PIN);  in gpio_regs_show()
488 		gpio_seq_reg(s, chip, "Data", JZ_REG_GPIO_DATA);  in gpio_regs_show()
489 		gpio_seq_reg(s, chip, "Mask", JZ_REG_GPIO_MASK);  in gpio_regs_show()
490 		gpio_seq_reg(s, chip, "Pull", JZ_REG_GPIO_PULL);  in gpio_regs_show()
491 		gpio_seq_reg(s, chip, "Func", JZ_REG_GPIO_FUNC);  in gpio_regs_show()
492 		gpio_seq_reg(s, chip, "Select", JZ_REG_GPIO_SELECT);  in gpio_regs_show()
493 		gpio_seq_reg(s, chip, "Direction", JZ_REG_GPIO_DIRECTION);  in gpio_regs_show()
494 		gpio_seq_reg(s, chip, "Trigger", JZ_REG_GPIO_TRIGGER);  in gpio_regs_show()
495 		gpio_seq_reg(s, chip, "Flag", JZ_REG_GPIO_FLAG);  in gpio_regs_show()